Typedefs

verilog-ts-mode

This feature is not needed if using verilog-ts-mode as it is able to parse any data type.

Background

This feature automates the process of extracting typedefs/classes from a set of files in directories and update variables to improve syntax highlighting and declaration alignment.

By default verilog-pretty-declarations and verilog-pretty-expr will only align built-in types. If you want it to also work on user defined types it is needed to specify which are those types. This feature automates the process of extracting current project typedefs.

Configuration

First make sure that typedefs has been included in verilog-ext-feature-list before running verilog-ext-mode-setup.

Next set the variable verilog-ext-project-alist:

(setq verilog-ext-project-alist
      `(("ucontroller"
         :root "/home/gonz/Repos/larumbe/ucontroller"
         :files ("src/pkg/global_pkg.sv"
                 "src/alu/rtl/alu.sv"
                 "src/misc/rtl/bin2bcd.sv"
                 "src/cpu/rtl/cpu.sv"
                 "src/dma/rtl/dma.sv"
                 "src/dma/rtl/dma_arbiter.sv"
                 "src/dma/rtl/dma_rx.sv"
                 "src/dma/rtl/dma_tx.sv"
                 "src/uart/rtl/fifo_wrapper.sv"
                 "src/ram/rtl/gp_ram.sv"
                 "src/ram/rtl/ram.sv"
                 "src/top/rtl/ram_arbiter.sv"
                 "src/ram/rtl/regs_ram.sv"
                 "src/uart/rtl/sreg.sv"
                 "src/uart/rtl/uart.sv"
                 "src/uart/rtl/uart_rx.sv"
                 "src/uart/rtl/uart_tx.sv"
                 "src/top/rtl/ucontroller.sv"
                 "src/uart/tb/fifo_generator_0_sim_netlist.v"
                 "src/top/tb/tb_clocks.sv"
                 "src/top/tb/tb_program.sv"
                 "src/top/tb/tb_top.sv"
                 "src/dma/tb/tb_dma.sv"
                 "src/alu/tb/tb_alu.sv"
                 "src/misc/tb/tb_bin2bcd.sv"
                 "src/cpu/tb/tb_cpu.sv"
                 "src/ram/tb/tb_ram.sv"
                 "src/uart/tb/tb_uart.sv")
         :ignore-files ("src/uart/tb/fifo_generator_0_sim_netlist.v")
         :compile-cmd "make tb_top" ; command used to compile current project
         ;; `vhier' related properties
         :command-file nil       ; vhier command file
         :lib-search-path nil))) ; list of dirs to look for include directories or libraries

To gather project typedefs run one of these functions:

• M-x verilog-ext-typedef-get RET
• M-x verilog-ext-typedef-get-async RET

A typedef database will be created and cached for future sessions.

At this point, two new things should be working:

• User types and class object declarations should be highlighted
• Running verilog-pretty-declarations should also align these types