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Added Quartus projct file for example design, removed some resets, BUSY changed to DIN_RDY.
1 parent 9fb8e9e commit f624c86

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-109
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‎README.md

Lines changed: 13 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -12,19 +12,16 @@ The UART controller was simulated and tested in hardware.
1212
-- CLOCK AND RESET
1313
CLK : in std_logic; -- system clock
1414
RST : in std_logic; -- high active synchronous reset
15-
1615
-- UART INTERFACE
1716
UART_TXD : out std_logic; -- serial transmit data
1817
UART_RXD : in std_logic; -- serial receive data
19-
2018
-- USER DATA INPUT INTERFACE
21-
DIN : in std_logic_vector(7 downto 0); -- data to be transmitted over UART
22-
DIN_VLD : in std_logic; -- when DIN_VLD = 1, DIN is valid and will be accepted for transmiting
23-
BUSY : out std_logic; -- when BUSY = 1, transmitter is busy and DIN can not be accepted
24-
19+
DIN : in std_logic_vector(7 downto 0); -- input data to be transmitted over UART
20+
DIN_VLD : in std_logic; -- when DIN_VLD = 1, input data (DIN) are valid
21+
DIN_RDY : out std_logic -- when DIN_RDY = 1, transmitter is ready and valid input data will be accepted for transmiting
2522
-- USER DATA OUTPUT INTERFACE
26-
DOUT : out std_logic_vector(7 downto 0); -- data received via UART
27-
DOUT_VLD : out std_logic; -- when DOUT_VLD = 1, DOUT is valid (is assert only for one clock cycle)
23+
DOUT : out std_logic_vector(7 downto 0); -- output data received via UART
24+
DOUT_VLD : out std_logic; -- when DOUT_VLD = 1, output data (DOUT) are valid (is assert only for one clock cycle)
2825
FRAME_ERROR : out std_logic -- when FRAME_ERROR = 1, stop bit was invalid (is assert only for one clock cycle)
2926
```
3027

@@ -41,14 +38,14 @@ USE_DEBOUNCER : boolean := True -- enable/disable debouncer
4138

4239
Use debouncer | Parity type | LE (LUT+FF) | LUT | FF | BRAM | Fmax
4340
:---:|:---:|:---:|:---:|:---:|:---:|:---:
44-
True | none | 77 | 64 | 55 | 0 | 202.2 MHz
45-
True | even/odd | 82 | 75 | 58 | 0 | 162.5 MHz
46-
True | mark/space | 80 | 68 | 58 | 0 | 184.5 MHz
47-
False | none | 72 | 59 | 50 | 0 | 182.7 MHz
48-
False | even/odd | 77 | 70 | 53 | 0 | 155.6 MHz
49-
False | mark/space | 75 | 62 | 53 | 0 | 200.8 MHz
50-
51-
*Synthesis was performed using Quartus II 64-Bit Version 13.0.1 for FPGA Altera Cyclone II with enable force use of synchronous clear. Setting of some generics: BAUD_RATE = 115200, CLK_FREQ = 50e6.*
41+
True | none | 74 | 59 | 53 | 0 | 220.0 MHz
42+
True | even/odd | 81 | 70 | 56 | 0 | 193.3 MHz
43+
True | mark/space | 78 | 63 | 56 | 0 | 210.2 MHz
44+
False | none | 70 | 57 | 49 | 0 | 182.3 MHz
45+
False | even/odd | 78 | 68 | 52 | 0 | 183.5 MHz
46+
False | mark/space | 74 | 61 | 52 | 0 | 186.2 MHz
47+
48+
*Implementation was performed using Quartus Prime Lite Edition 17.0.0 for FPGA Altera Cyclone IV E EP4CE6E22C8. Setting of some generics: BAUD_RATE = 115200, CLK_FREQ = 50e6.*
5249

5350
# Simulation:
5451

‎example/ep4ce6_starter_board_assignments.qsf

Lines changed: 0 additions & 22 deletions
This file was deleted.

‎example/quartus/uart_loopback.qpf

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
#-------------------------------------------------------------------------------
2+
# PROJECT: SIMPLE UART FOR FPGA
3+
#-------------------------------------------------------------------------------
4+
# NAME: QUARTUS PROJECT FILE
5+
# AUTHORS: Jakub Cabal <[email protected]>
6+
# LICENSE: The MIT License (MIT), please read LICENSE file
7+
# WEBSITE: https://github.com/jakubcabal/uart-for-fpga
8+
#-------------------------------------------------------------------------------
9+
10+
PROJECT_REVISION = "uart_loopback"

‎example/quartus/uart_loopback.qsf

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
#-------------------------------------------------------------------------------
2+
# PROJECT: SIMPLE UART FOR FPGA
3+
#-------------------------------------------------------------------------------
4+
# NAME: QUARTUS SETTINGS FILE FOR EP4CE6 STARTER BOARD
5+
# AUTHORS: Jakub Cabal <[email protected]>
6+
# LICENSE: The MIT License (MIT), please read LICENSE file
7+
# WEBSITE: https://github.com/jakubcabal/uart-for-fpga
8+
#-------------------------------------------------------------------------------
9+
10+
set_global_assignment -name FAMILY "Cyclone IV E"
11+
set_global_assignment -name DEVICE EP4CE6E22C8
12+
set_global_assignment -name TOP_LEVEL_ENTITY UART_LOOPBACK
13+
14+
# PROJECT VHDL FILES
15+
set_global_assignment -name VHDL_FILE ../uart_loopback.vhd
16+
set_global_assignment -name VHDL_FILE ../../rtl/uart.vhd
17+
set_global_assignment -name VHDL_FILE ../../rtl/comp/uart_tx.vhd
18+
set_global_assignment -name VHDL_FILE ../../rtl/comp/uart_rx.vhd
19+
set_global_assignment -name VHDL_FILE ../../rtl/comp/uart_parity.vhd
20+
set_global_assignment -name VHDL_FILE ../../rtl/comp/uart_debouncer.vhd
21+
22+
# TIMING CONSTRAINTS
23+
set_global_assignment -name SDC_FILE ../timing_constraints.sdc
24+
25+
# FPGA PINS ASSIGNMENT FOR EP4CE6 STARTER BOARD
26+
set_location_assignment PIN_91 -to CLK
27+
set_location_assignment PIN_25 -to RST
28+
set_location_assignment PIN_85 -to UART_TXD
29+
set_location_assignment PIN_86 -to UART_RXD

‎example/uart_loopback.vhd

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ begin
5757
-- USER DATA INPUT INTERFACE
5858
DIN => data,
5959
DIN_VLD => valid,
60-
BUSY => open
60+
DIN_RDY => open
6161
);
6262

6363
end FULL;

‎example/uart_loopback_tb.vhd

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -17,10 +17,10 @@ end UART_LOOPBACK_TB;
1717
architecture FULL of UART_LOOPBACK_TB is
1818

1919
signal CLK : std_logic := '0';
20-
signal RST_N : std_logic := '0';
20+
signal RST : std_logic := '1';
2121
signal tx_uart : std_logic;
2222
signal rx_uart : std_logic := '1';
23-
signal busy : std_logic;
23+
signal din_rdy : std_logic;
2424
signal frame_error : std_logic;
2525

2626
constant clk_period : time := 20 ns;
@@ -38,12 +38,12 @@ begin
3838
)
3939
port map (
4040
CLK => CLK,
41-
RST_N => RST_N,
41+
RST => RST,
4242
-- UART INTERFACE
4343
UART_TXD => tx_uart,
4444
UART_RXD => rx_uart,
4545
-- DEBUG INTERFACE
46-
BUSY => busy,
46+
DIN_RDY => din_rdy,
4747
FRAME_ERR => frame_error
4848
);
4949

@@ -58,9 +58,9 @@ begin
5858
test_rx_uart : process
5959
begin
6060
rx_uart <= '1';
61-
RST_N <= '0';
61+
RST <= '1';
6262
wait for 100 ns;
63-
RST_N <= '1';
63+
RST <= '0';
6464

6565
wait for uart_period;
6666

‎rtl/comp/debouncer.vhd renamed to ‎rtl/comp/uart_debouncer.vhd

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
--------------------------------------------------------------------------------
22
-- PROJECT: SIMPLE UART FOR FPGA
33
--------------------------------------------------------------------------------
4-
-- MODULE: DEBOUNCER
4+
-- MODULE: UART DEBOUNCER
55
-- AUTHORS: Jakub Cabal <[email protected]>
66
-- LICENSE: The MIT License (MIT), please read LICENSE file
77
-- WEBSITE: https://github.com/jakubcabal/uart-for-fpga
@@ -11,7 +11,7 @@ library IEEE;
1111
use IEEE.STD_LOGIC_1164.ALL;
1212
use IEEE.NUMERIC_STD.ALL;
1313

14-
entity DEBOUNCER is
14+
entity UART_DEBOUNCER is
1515
Generic (
1616
-- latency of debouncer in clock cycles, minimum value is 2,
1717
-- value also corresponds to the number of bits compared
@@ -22,9 +22,9 @@ entity DEBOUNCER is
2222
DEB_IN : in std_logic; -- input of signal from outside FPGA
2323
DEB_OUT : out std_logic -- output of debounced (filtered) signal
2424
);
25-
end DEBOUNCER;
25+
end UART_DEBOUNCER;
2626

27-
architecture RTL of DEBOUNCER is
27+
architecture RTL of UART_DEBOUNCER is
2828

2929
constant SHREG_DEPTH : natural := LATENCY-1;
3030

‎rtl/comp/uart_rx.vhd

Lines changed: 25 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -22,8 +22,8 @@ entity UART_RX is
2222
UART_CLK_EN : in std_logic; -- oversampling (16x) UART clock enable
2323
UART_RXD : in std_logic; -- serial receive data
2424
-- USER DATA OUTPUT INTERFACE
25-
DOUT : out std_logic_vector(7 downto 0); -- data received via UART
26-
DOUT_VLD : out std_logic; -- when DOUT_VLD = 1, DOUT is valid (is assert only for one clock cycle)
25+
DOUT : out std_logic_vector(7 downto 0); -- output data received via UART
26+
DOUT_VLD : out std_logic; -- when DOUT_VLD = 1, output data (DOUT) are valid (is assert only for one clock cycle)
2727
FRAME_ERROR : out std_logic -- when FRAME_ERROR = 1, stop bit was invalid (is assert only for one clock cycle)
2828
);
2929
end UART_RX;
@@ -55,7 +55,7 @@ begin
5555
begin
5656
if (rising_edge(CLK)) then
5757
if (rx_clk_divider_en = '1') then
58-
if (uart_clk_en = '1') then
58+
if (UART_CLK_EN = '1') then
5959
if (rx_ticks = "1111") then
6060
rx_ticks <= (others => '0');
6161
else
@@ -75,7 +75,7 @@ begin
7575
if (rising_edge(CLK)) then
7676
if (RST = '1') then
7777
rx_clk_en <= '0';
78-
elsif (uart_clk_en = '1' AND rx_ticks = "0111") then
78+
elsif (UART_CLK_EN = '1' AND rx_ticks = "0111") then
7979
rx_clk_en <= '1';
8080
else
8181
rx_clk_en <= '0';
@@ -109,9 +109,7 @@ begin
109109
uart_rx_data_shift_reg_p : process (CLK)
110110
begin
111111
if (rising_edge(CLK)) then
112-
if (RST = '1') then
113-
rx_data <= (others => '0');
114-
elsif (rx_clk_en = '1' AND rx_receiving_data = '1') then
112+
if (rx_clk_en = '1' AND rx_receiving_data = '1') then
115113
rx_data <= UART_RXD & rx_data(7 downto 1);
116114
end if;
117115
end if;
@@ -137,9 +135,7 @@ begin
137135
uart_rx_parity_check_reg_p : process (CLK)
138136
begin
139137
if (rising_edge(CLK)) then
140-
if (RST = '1') then
141-
rx_parity_error <= '0';
142-
elsif (rx_parity_check_en = '1') then
138+
if (rx_clk_en = '1') then
143139
rx_parity_error <= rx_parity_bit XOR UART_RXD;
144140
end if;
145141
end if;
@@ -194,10 +190,9 @@ begin
194190
case rx_pstate is
195191

196192
when idle =>
197-
rx_output_reg_en <= '0';
198-
rx_receiving_data <= '0';
199-
rx_clk_divider_en <= '0';
200-
rx_parity_check_en <= '0';
193+
rx_output_reg_en <= '0';
194+
rx_receiving_data <= '0';
195+
rx_clk_divider_en <= '0';
201196

202197
if (UART_RXD = '0') then
203198
rx_nstate <= startbit;
@@ -206,10 +201,9 @@ begin
206201
end if;
207202

208203
when startbit =>
209-
rx_output_reg_en <= '0';
210-
rx_receiving_data <= '0';
211-
rx_clk_divider_en <= '1';
212-
rx_parity_check_en <= '0';
204+
rx_output_reg_en <= '0';
205+
rx_receiving_data <= '0';
206+
rx_clk_divider_en <= '1';
213207

214208
if (rx_clk_en = '1') then
215209
rx_nstate <= databits;
@@ -218,10 +212,9 @@ begin
218212
end if;
219213

220214
when databits =>
221-
rx_output_reg_en <= '0';
222-
rx_receiving_data <= '1';
223-
rx_clk_divider_en <= '1';
224-
rx_parity_check_en <= '0';
215+
rx_output_reg_en <= '0';
216+
rx_receiving_data <= '1';
217+
rx_clk_divider_en <= '1';
225218

226219
if ((rx_clk_en = '1') AND (rx_bit_count = "111")) then
227220
if (PARITY_BIT = "none") then
@@ -234,10 +227,9 @@ begin
234227
end if;
235228

236229
when paritybit =>
237-
rx_output_reg_en <= '0';
238-
rx_receiving_data <= '0';
239-
rx_clk_divider_en <= '1';
240-
rx_parity_check_en <= '1';
230+
rx_output_reg_en <= '0';
231+
rx_receiving_data <= '0';
232+
rx_clk_divider_en <= '1';
241233

242234
if (rx_clk_en = '1') then
243235
rx_nstate <= stopbit;
@@ -246,10 +238,9 @@ begin
246238
end if;
247239

248240
when stopbit =>
249-
rx_receiving_data <= '0';
250-
rx_clk_divider_en <= '1';
251-
rx_parity_check_en <= '0';
252-
rx_output_reg_en <= '1';
241+
rx_output_reg_en <= '1';
242+
rx_receiving_data <= '0';
243+
rx_clk_divider_en <= '1';
253244

254245
if (rx_clk_en = '1') then
255246
rx_nstate <= idle;
@@ -258,11 +249,10 @@ begin
258249
end if;
259250

260251
when others =>
261-
rx_output_reg_en <= '0';
262-
rx_receiving_data <= '0';
263-
rx_clk_divider_en <= '0';
264-
rx_parity_check_en <= '0';
265-
rx_nstate <= idle;
252+
rx_output_reg_en <= '0';
253+
rx_receiving_data <= '0';
254+
rx_clk_divider_en <= '0';
255+
rx_nstate <= idle;
266256

267257
end case;
268258
end process;

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