[AMDGPU] gfx1250: MC support for 64-bit literals #147861
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@llvm/pr-subscribers-backend-amdgpu @llvm/pr-subscribers-mc Author: Stanislav Mekhanoshin (rampitec) ChangesPatch is 105.40 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/147861.diff 16 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 55077a94f09a1..91ace4d2b7f16 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1130,6 +1130,12 @@ def FeaturePointSampleAccel : SubtargetFeature<"point-sample-accel",
"Has point sample acceleration feature"
>;
+def Feature64BitLiterals : SubtargetFeature<"64-bit-literals",
+ "Has64BitLiterals",
+ "true",
+ "Can use 64-bit literals with single DWORD instructions"
+>;
+
def FeatureWaitXcnt : SubtargetFeature<"wait-xcnt",
"HasWaitXcnt",
"true",
@@ -1931,6 +1937,7 @@ def FeatureISAVersion12_50 : FeatureSet<
[FeatureGFX12,
FeatureGFX1250Insts,
FeatureCuMode,
+ Feature64BitLiterals,
FeatureLDSBankCount32,
FeatureDLInsts,
FeatureFmacF64Inst,
@@ -2678,6 +2685,9 @@ def HasPrngInst : Predicate<"Subtarget->hasPrngInst()">,
def HasBVHDualAndBVH8Insts : Predicate<"Subtarget->hasBVHDualAndBVH8Insts()">,
AssemblerPredicate<(all_of FeatureBVHDualAndBVH8Insts)>;
+def Has64BitLiterals : Predicate<"Subtarget->has64BitLiterals()">,
+ AssemblerPredicate<(all_of Feature64BitLiterals)>;
+
def HasWaitXcnt : Predicate<"Subtarget->hasWaitXcnt()">,
AssemblerPredicate<(all_of FeatureWaitXcnt)>;
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 3af140461afdb..673dc5c9a9ea6 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -81,6 +81,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
bool Neg = false;
bool Sext = false;
bool Lit = false;
+ bool Lit64 = false;
bool hasFPModifiers() const { return Abs || Neg; }
bool hasIntModifiers() const { return Sext; }
@@ -480,7 +481,10 @@ class AMDGPUOperand : public MCParsedAsmOperand {
bool isSSrc_b64() const {
// TODO: Find out how SALU supports extension of 32-bit literals to 64 bits.
// See isVSrc64().
- return isSCSrc_b64() || isLiteralImm(MVT::i64);
+ return isSCSrc_b64() || isLiteralImm(MVT::i64) ||
+ (((const MCTargetAsmParser *)AsmParser)
+ ->getAvailableFeatures()[AMDGPU::Feature64BitLiterals] &&
+ isExpr());
}
bool isSSrc_f32() const {
@@ -1537,6 +1541,10 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
return getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm];
}
+ bool has64BitLiterals() const {
+ return getFeatureBits()[AMDGPU::Feature64BitLiterals];
+ }
+
bool hasFlatOffsets() const {
return getFeatureBits()[AMDGPU::FeatureFlatInstOffsets];
}
@@ -1663,10 +1671,10 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool isOpcodeModifierWithVal(const AsmToken &Token, const AsmToken &NextToken) const;
bool parseSP3NegModifier();
ParseStatus parseImm(OperandVector &Operands, bool HasSP3AbsModifier = false,
- bool HasLit = false);
+ bool HasLit = false, bool HasLit64 = false);
ParseStatus parseReg(OperandVector &Operands);
ParseStatus parseRegOrImm(OperandVector &Operands, bool HasSP3AbsMod = false,
- bool HasLit = false);
+ bool HasLit = false, bool HasLit64 = false);
ParseStatus parseRegOrImmWithFPInputMods(OperandVector &Operands,
bool AllowImm = true);
ParseStatus parseRegOrImmWithIntInputMods(OperandVector &Operands,
@@ -2123,6 +2131,9 @@ bool AMDGPUOperand::isLiteralImm(MVT type) const {
return false;
}
+ bool Allow64Bit = (type == MVT::i64 || type == MVT::f64) &&
+ AsmParser->has64BitLiterals();
+
if (!Imm.IsFPImm) {
// We got int literal token.
@@ -2134,8 +2145,11 @@ bool AMDGPUOperand::isLiteralImm(MVT type) const {
}
unsigned Size = type.getSizeInBits();
- if (Size == 64)
+ if (Size == 64) {
+ if (Allow64Bit && !AMDGPU::isValid32BitLiteral(Imm.Val, false))
+ return true;
Size = 32;
+ }
// FIXME: 64-bit operands can zero extend, sign extend, or pad zeroes for FP
// types.
@@ -2287,12 +2301,18 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
}
// Non-inlineable
- if (AMDGPU::isSISrcFPOperand(InstDesc, OpNum)) { // Expected 64-bit fp operand
+ if (AMDGPU::isSISrcFPOperand(InstDesc,
+ OpNum)) { // Expected 64-bit fp operand
+ bool HasMandatoryLiteral =
+ AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::imm);
// For fp operands we check if low 32 bits are zeros
- if (Literal.getLoBits(32) != 0) {
- const_cast<AMDGPUAsmParser *>(AsmParser)->Warning(Inst.getLoc(),
- "Can't encode literal as exact 64-bit floating-point operand. "
- "Low 32-bits will be set to zero");
+ if (Literal.getLoBits(32) != 0 &&
+ (InstDesc.getSize() != 4 || !AsmParser->has64BitLiterals()) &&
+ !HasMandatoryLiteral) {
+ const_cast<AMDGPUAsmParser *>(AsmParser)->Warning(
+ Inst.getLoc(),
+ "Can't encode literal as exact 64-bit floating-point operand. "
+ "Low 32-bits will be set to zero");
Val &= 0xffffffff00000000u;
}
@@ -2392,8 +2412,25 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
return;
case AMDGPU::OPERAND_REG_IMM_INT64:
- case AMDGPU::OPERAND_REG_IMM_FP64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
+ if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) {
+ Inst.addOperand(MCOperand::createImm(Val));
+ setImmKindConst();
+ return;
+ }
+
+ // When the 32 MSBs are not zero (effectively means it can't be safely
+ // truncated to uint32_t), if the target doesn't support 64-bit literals, or
+ // the lit modifier is explicitly used, we need to truncate it to the 32
+ // LSBs.
+ if (!AsmParser->has64BitLiterals() || getModifiers().Lit)
+ Val = Lo_32(Val);
+
+ Inst.addOperand(MCOperand::createImm(Val));
+ setImmKindLiteral();
+ return;
+
+ case AMDGPU::OPERAND_REG_IMM_FP64:
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) {
@@ -2402,8 +2439,20 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
return;
}
- Val = AMDGPU::isSISrcFPOperand(InstDesc, OpNum) ? (uint64_t)Val << 32
- : Lo_32(Val);
+ // If the target doesn't support 64-bit literals, we need to use the
+ // constant as the high 32 MSBs of a double-precision floating point value.
+ if (!AsmParser->has64BitLiterals()) {
+ Val = static_cast<uint64_t>(Val) << 32;
+ } else {
+ // Now the target does support 64-bit literals, there are two cases
+ // where we still want to use src_literal encoding:
+ // 1) explicitly forced by using lit modifier;
+ // 2) the value is a valid 32-bit representation (signed or unsigned),
+ // meanwhile not forced by lit64 modifier.
+ if (getModifiers().Lit ||
+ (!getModifiers().Lit64 && (isInt<32>(Val) || isUInt<32>(Val))))
+ Val = static_cast<uint64_t>(Val) << 32;
+ }
Inst.addOperand(MCOperand::createImm(Val));
setImmKindLiteral();
@@ -3151,19 +3200,20 @@ AMDGPUAsmParser::parseRegister(bool RestoreOnFailure) {
}
ParseStatus AMDGPUAsmParser::parseImm(OperandVector &Operands,
- bool HasSP3AbsModifier, bool HasLit) {
+ bool HasSP3AbsModifier, bool HasLit,
+ bool HasLit64) {
// TODO: add syntactic sugar for 1/(2*PI)
- if (isRegister())
+ if (isRegister() || isModifier())
return ParseStatus::NoMatch;
- assert(!isModifier());
- if (!HasLit) {
- HasLit = trySkipId("lit");
- if (HasLit) {
+ if (!HasLit && !HasLit64) {
+ HasLit64 = trySkipId("lit64");
+ HasLit = !HasLit64 && trySkipId("lit");
+ if (HasLit || HasLit64) {
if (!skipToken(AsmToken::LParen, "expected left paren after lit"))
return ParseStatus::Failure;
- ParseStatus S = parseImm(Operands, HasSP3AbsModifier, HasLit);
+ ParseStatus S = parseImm(Operands, HasSP3AbsModifier, HasLit, HasLit64);
if (S.isSuccess() &&
!skipToken(AsmToken::RParen, "expected closing parentheses"))
return ParseStatus::Failure;
@@ -3185,6 +3235,7 @@ ParseStatus AMDGPUAsmParser::parseImm(OperandVector &Operands,
AMDGPUOperand::Modifiers Mods;
Mods.Lit = HasLit;
+ Mods.Lit64 = HasLit64;
if (IsReal) {
// Floating-point expressions are not supported.
@@ -3235,7 +3286,7 @@ ParseStatus AMDGPUAsmParser::parseImm(OperandVector &Operands,
AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
Op.setModifiers(Mods);
} else {
- if (HasLit)
+ if (HasLit || HasLit64)
return ParseStatus::NoMatch;
Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S));
}
@@ -3259,13 +3310,14 @@ ParseStatus AMDGPUAsmParser::parseReg(OperandVector &Operands) {
}
ParseStatus AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands,
- bool HasSP3AbsMod, bool HasLit) {
+ bool HasSP3AbsMod, bool HasLit,
+ bool HasLit64) {
ParseStatus Res = parseReg(Operands);
if (!Res.isNoMatch())
return Res;
if (isModifier())
return ParseStatus::NoMatch;
- return parseImm(Operands, HasSP3AbsMod, HasLit);
+ return parseImm(Operands, HasSP3AbsMod, HasLit, HasLit64);
}
bool
@@ -3361,7 +3413,7 @@ AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands,
bool AllowImm) {
bool Neg, SP3Neg;
bool Abs, SP3Abs;
- bool Lit;
+ bool Lit64, Lit;
SMLoc Loc;
// Disable ambiguous constructs like '--1' etc. Should use neg(-1) instead.
@@ -3381,7 +3433,15 @@ AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands,
if (Abs && !skipToken(AsmToken::LParen, "expected left paren after abs"))
return ParseStatus::Failure;
- Lit = trySkipId("lit");
+ Lit64 = trySkipId("lit64");
+ if (Lit64) {
+ if (!skipToken(AsmToken::LParen, "expected left paren after lit64"))
+ return ParseStatus::Failure;
+ if (!has64BitLiterals())
+ return Error(Loc, "lit64 is not supported on this GPU");
+ }
+
+ Lit = !Lit64 && trySkipId("lit");
if (Lit && !skipToken(AsmToken::LParen, "expected left paren after lit"))
return ParseStatus::Failure;
@@ -3392,14 +3452,15 @@ AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands,
ParseStatus Res;
if (AllowImm) {
- Res = parseRegOrImm(Operands, SP3Abs, Lit);
+ Res = parseRegOrImm(Operands, SP3Abs, Lit, Lit64);
} else {
Res = parseReg(Operands);
}
if (!Res.isSuccess())
- return (SP3Neg || Neg || SP3Abs || Abs || Lit) ? ParseStatus::Failure : Res;
+ return (SP3Neg || Neg || SP3Abs || Abs || Lit || Lit64) ?
+ ParseStatus::Failure : Res;
- if (Lit && !Operands.back()->isImm())
+ if ((Lit || Lit64) && !Operands.back()->isImm())
Error(Loc, "expected immediate with lit modifier");
if (SP3Abs && !skipToken(AsmToken::Pipe, "expected vertical bar"))
@@ -3408,15 +3469,17 @@ AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands,
return ParseStatus::Failure;
if (Neg && !skipToken(AsmToken::RParen, "expected closing parentheses"))
return ParseStatus::Failure;
- if (Lit && !skipToken(AsmToken::RParen, "expected closing parentheses"))
+ if ((Lit || Lit64) &&
+ !skipToken(AsmToken::RParen, "expected closing parentheses"))
return ParseStatus::Failure;
AMDGPUOperand::Modifiers Mods;
Mods.Abs = Abs || SP3Abs;
Mods.Neg = Neg || SP3Neg;
Mods.Lit = Lit;
+ Mods.Lit64 = Lit64;
- if (Mods.hasFPModifiers() || Lit) {
+ if (Mods.hasFPModifiers() || Lit || Lit64) {
AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
if (Op.isExpr())
return Error(Op.getStartLoc(), "expected an absolute expression");
@@ -4588,7 +4651,7 @@ bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst) const {
unsigned NumExprs = 0;
unsigned NumLiterals = 0;
- uint32_t LiteralValue;
+ uint64_t LiteralValue;
for (int OpIdx : OpIndices) {
if (OpIdx == -1) break;
@@ -4597,7 +4660,7 @@ bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst) const {
// Exclude special imm operands (like that used by s_set_gpr_idx_on)
if (AMDGPU::isSISrcOperand(Desc, OpIdx)) {
if (MO.isImm() && !isInlineConstant(Inst, OpIdx)) {
- uint32_t Value = static_cast<uint32_t>(MO.getImm());
+ uint64_t Value = static_cast<uint64_t>(MO.getImm());
if (NumLiterals == 0 || LiteralValue != Value) {
LiteralValue = Value;
++NumLiterals;
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 59c72fcbff18a..8cea324f706c2 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -1484,6 +1484,20 @@ MCOperand AMDGPUDisassembler::decodeLiteralConstant(bool ExtendFP64) const {
return MCOperand::createImm(ExtendFP64 ? Literal64 : Literal);
}
+MCOperand AMDGPUDisassembler::decodeLiteral64Constant() const {
+ assert(STI.hasFeature(AMDGPU::Feature64BitLiterals));
+
+ if (!HasLiteral) {
+ if (Bytes.size() < 8) {
+ return errOperand(0, "cannot read literal64, inst bytes left " +
+ Twine(Bytes.size()));
+ }
+ HasLiteral = true;
+ Literal64 = eatBytes<uint64_t>(Bytes);
+ }
+ return MCOperand::createImm(Literal64);
+}
+
MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
using namespace AMDGPU::EncValues;
@@ -1767,6 +1781,10 @@ MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp(unsigned Width,
Val == LITERAL_CONST)
return MCOperand::createImm(Val);
+ if (Val == LITERAL64_CONST && STI.hasFeature(AMDGPU::Feature64BitLiterals)) {
+ return decodeLiteral64Constant();
+ }
+
switch (Width) {
case 32:
case 16:
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
index 0fe487ff26fc1..8927f208fd2af 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
@@ -179,6 +179,7 @@ class AMDGPUDisassembler : public MCDisassembler {
MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const;
MCOperand decodeLiteralConstant(bool ExtendFP64) const;
+ MCOperand decodeLiteral64Constant() const;
MCOperand decodeSrcOp(unsigned Width, unsigned Val) const;
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index fa1209db2fa07..acdd369f17925 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -231,6 +231,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
bool HasSALUFloatInsts = false;
bool HasPseudoScalarTrans = false;
bool HasRestrictedSOffset = false;
+ bool Has64BitLiterals = false;
bool HasBitOp3Insts = false;
bool HasTransposeLoadF4F6Insts = false;
bool HasPrngInst = false;
@@ -1384,6 +1385,9 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
/// GFX1250.
bool hasWaitXCnt() const { return HasWaitXcnt; }
+ // A single DWORD instructions can use a 64-bit literal.
+ bool has64BitLiterals() const { return Has64BitLiterals; }
+
bool hasPointSampleAccel() const { return HasPointSampleAccel; }
bool hasLdsBarrierArriveAtomic() const { return HasLdsBarrierArriveAtomic; }
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index fa1474d153834..8ce12dfeda779 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -604,15 +604,21 @@ void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
else if (Imm == 0x3fc45f306dc9c882 &&
STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
O << "0.15915494309189532";
- else if (IsFP) {
- assert(AMDGPU::isValid32BitLiteral(Imm, true));
- O << formatHex(static_cast<uint64_t>(Hi_32(Imm)));
- } else {
- assert(isUInt<32>(Imm) || isInt<32>(Imm));
+ else {
+ // This part needs to align with AMDGPUOperand::addLiteralImmOperand.
+ if (IsFP) {
+ if (STI.hasFeature(AMDGPU::Feature64BitLiterals) && Lo_32(Imm))
+ O << "lit64(" << formatHex(static_cast<uint64_t>(Imm)) << ')';
+ else
+ O << formatHex(static_cast<uint64_t>(Hi_32(Imm)));
+ return;
+ }
- // In rare situations, we will have a 32-bit literal in a 64-bit
- // operand. This is technically allowed for the encoding of s_mov_b64.
- O << formatHex(static_cast<uint64_t>(Imm));
+ if (STI.hasFeature(AMDGPU::Feature64BitLiterals) &&
+ (!isInt<32>(Imm) || !isUInt<32>(Imm)))
+ O << "lit64(" << formatHex(static_cast<uint64_t>(Imm)) << ')';
+ else
+ O << formatHex(static_cast<uint64_t>(Imm));
}
}
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
index 086f980f5fe23..13ab00beddc9b 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
@@ -218,7 +218,8 @@ static uint32_t getLit16IntEncoding(uint32_t Val, const MCSubtargetInfo &STI) {
return getLit32Encoding(Val, STI);
}
-static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI) {
+static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI,
+ bool IsFP) {
uint32_t IntImm = getIntInlineImmEncoding(static_cast<int64_t>(Val));
if (IntImm != 0)
return IntImm;
@@ -251,6 +252,18 @@ static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI) {
STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
return 248;
+ // The rest part needs to align with AMDGPUInstPrinter::printImmediate64.
+
+ if (IsFP) {
+ return STI.hasFeature(AMDGPU::Feature64BitLiterals) && Lo_32(Val) ? 254
+ : 255;
+ }
+
+ return STI.hasFeature(AMDGPU::Feature64BitLiterals) &&
+ (!isInt<32>(Val) || !isUInt<32>(Val))
+ ? 254
+ : 255;
+
return 255;
}
@@ -261,7 +274,10 @@ AMDGPUMCCodeEmitter::getLitEncoding(const MCOperand &MO,
int64_t Imm;
if (MO.isExpr()) {
if (!MO.getExpr()->evaluateAsAbsolute(Imm))
- return 255;
+ return (STI.hasFeature(AMDGPU::Feature64BitLiterals) &&
+ OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_INT64)
+ ? 254
+ : 255;
} else {
assert(!MO.isDFPImm());
@@ -284,11 +300,13 @@ AMDGPUMCCodeEmitter::getLitEncoding(const MCOperand &MO,
return getLit32Encoding(static_cast<uint32_t>(Imm), STI);
case AMDGPU::OPERAND_REG_IMM_INT64:
- case AMDGPU::OPERAND_REG_IMM_FP64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
+ return getLit64Encoding(static_cast<uint64_t>(Imm), STI, false);
+
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
- return getLit64Encoding(static_cast<uint64_t>(Imm), STI);
+ case AMDGPU::OPERAND_REG_IMM_FP64:
+ return getLit64Encoding(static_cast<uint64_t>(Imm), STI, true);
case AMDGPU::OPERAND_REG_IMM_INT16:
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
@@ -418,7 +436,7 @@ void AMDGPUMCCodeEmitter::encodeInstruction(const MCInst &MI,
// Is this operand a literal immediate?
const MCOperand &Op = MI.getOperand(i);
auto Enc = getLitEncoding(Op, Desc.operands()[i], STI);
- if (!Enc || *Enc != 255)
+ if (!Enc || (*Enc != 255 && *Enc != 254))
continue;
// Yes! Encode it
@@ -432,10 +450,14 @@ void AMDGPUMCCodeEmitter::encodeInstruction(c...
[truncated]
|
|
✅ With the latest revision this PR passed the C/C++ code formatter. |
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