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[RISCV] Handle LHS == 0 in isVLKnownLE #148860

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Merged
merged 1 commit into from
Jul 15, 2025
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[RISCV] Handle LHS == 0 in isVLKnownLE #148860

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2 changes: 2 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4812,6 +4812,8 @@ bool RISCV::isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS) {
return true;
if (RHS.isImm() && RHS.getImm() == RISCV::VLMaxSentinel)
return true;
if (LHS.isImm() && LHS.getImm() == 0)
return true;
if (LHS.isImm() && LHS.getImm() == RISCV::VLMaxSentinel)
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Not related to this patch, but LHS being RISCV::VLMaxSentinel doesn't rule out RHS also being dynamically VLMax does it? So they could still be equal. Is it correct to return false here?

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@lukel97 lukel97 Jul 16, 2025 •
edited
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This returns whether or not it's known to be LE, so I think returning false should be conservatively correct. I.e returning false != not LE

return false;
if (!LHS.isImm() || !RHS.isImm())
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5 changes: 3 additions & 2 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
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Expand Up @@ -439,9 +439,10 @@ define <256 x i8> @vsadd_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
define <256 x i8> @vsadd_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
; CHECK-LABEL: vsadd_vi_v258i8_evl128:
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 128
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v24, (a0)
; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
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Just to highlight - this means we're missing a bunch of combines on the VP nodes.

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@lukel97 lukel97 Jul 15, 2025 •
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Yeah, but I'm hoping that VP intrinsics with immediate EVLs are rare to begin with since they would need to be set to get.active.vector.length. And non trapping VP intrinsics in general, since the loop vectorizer doesn't emit them anymore!

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5 changes: 3 additions & 2 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
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Expand Up @@ -435,9 +435,10 @@ define <256 x i8> @vsaddu_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
define <256 x i8> @vsaddu_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
; CHECK-LABEL: vsaddu_vi_v258i8_evl128:
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 128
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v24, (a0)
; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
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11 changes: 6 additions & 5 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
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Expand Up @@ -454,14 +454,15 @@ define <256 x i8> @vssub_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
define <256 x i8> @vssub_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
; CHECK-LABEL: vssub_vi_v258i8_evl128:
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 128
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v24, (a0)
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
; CHECK-NEXT: li a0, 128
; CHECK-NEXT: li a1, -1
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
; CHECK-NEXT: vssub.vx v16, v16, a0, v0.t
; CHECK-NEXT: vssub.vx v16, v16, a1, v0.t
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)
ret <256 x i8> %v
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11 changes: 6 additions & 5 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
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Expand Up @@ -449,14 +449,15 @@ define <256 x i8> @vssubu_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
define <256 x i8> @vssubu_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) {
; CHECK-LABEL: vssubu_vi_v258i8_evl128:
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 128
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v24, (a0)
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
; CHECK-NEXT: li a0, 128
; CHECK-NEXT: li a1, -1
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetivli zero, 0, e8, m8, ta, ma
; CHECK-NEXT: vssubu.vx v16, v16, a0, v0.t
; CHECK-NEXT: vssubu.vx v16, v16, a1, v0.t
; CHECK-NEXT: ret
%v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128)
ret <256 x i8> %v
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