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[mlir][amdgpu] Add rocdl.s.waitcnt wrapper #149670

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23 changes: 23 additions & 0 deletions mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
Original file line number Diff line number Diff line change
Expand Up @@ -719,6 +719,29 @@ def AMDGPU_SchedBarrierOp :
}];
}

def AMDGPU_MemoryCounterWaitOp :
AMDGPU_Op<"memory_counter_wait">,
Arguments<(ins
OptionalAttr<I32Attr>:$load,
OptionalAttr<I32Attr>:$store,
OptionalAttr<I32Attr>:$ds,
OptionalAttr<I32Attr>:$exp
)>
{
let summary = "Wait for specified hardware counters";
let description = [{
Wait for the specified counters to be less-than or equal-to the provided
values before continuing.

Counters can lower to different instructions on different architectires,
including clamping to the some HW supported max value or combining multiple
counters into one.
}];
let assemblyFormat = [{
oilist( `load` `(` $load `)` | `store` `(` $store `)` | `ds` `(` $ds `)` | `exp` `(` $exp `)` ) attr-dict
}];
}

def AMDGPU_MFMAPermB : I32EnumAttr<"MFMAPermB",
"The possible permutations of the lanes storing B available in an MFMA",
[
Expand Down
112 changes: 109 additions & 3 deletions mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -419,6 +419,112 @@ struct RawBufferOpLowering : public ConvertOpToLLVMPattern<GpuOp> {
}
};

// TODO: AMDGPU backend already have all this bitpacking logic, we should move
// it to some common place.
/// Vmcnt, Expcnt and Lgkmcnt are decoded as follows:
/// Vmcnt = Waitcnt[3:0] (pre-gfx9)
/// Vmcnt = Waitcnt[15:14,3:0] (gfx9,10)
/// Vmcnt = Waitcnt[15:10] (gfx11)
/// Expcnt = Waitcnt[6:4] (pre-gfx11)
/// Expcnt = Waitcnt[2:0] (gfx11)
/// Lgkmcnt = Waitcnt[11:8] (pre-gfx10)
/// Lgkmcnt = Waitcnt[13:8] (gfx10)
/// Lgkmcnt = Waitcnt[9:4] (gfx11)
static FailureOr<unsigned> encodeWaitcnt(Chipset chipset, unsigned vmcnt,
unsigned expcnt, unsigned lgkmcnt) {
if (chipset.majorVersion < 9) {
vmcnt = std::min(15u, vmcnt);
expcnt = std::min(7u, expcnt);
lgkmcnt = std::min(15u, lgkmcnt);
return vmcnt | (expcnt << 4) | (lgkmcnt << 8);
}
if (chipset.majorVersion == 9) {
vmcnt = std::min(63u, vmcnt);
expcnt = std::min(7u, expcnt);
lgkmcnt = std::min(15u, lgkmcnt);
unsigned lowBits = vmcnt & 0xF;
unsigned highBits = (vmcnt >> 4) << 14;
unsigned otherCnts = (expcnt << 4) | (lgkmcnt << 8);
return lowBits | highBits | otherCnts;
}
if (chipset.majorVersion == 10) {
vmcnt = std::min(63u, vmcnt);
expcnt = std::min(7u, expcnt);
lgkmcnt = std::min(63u, lgkmcnt);
unsigned lowBits = vmcnt & 0xF;
unsigned highBits = (vmcnt >> 4) << 14;
unsigned otherCnts = (expcnt << 4) | (lgkmcnt << 8);
return lowBits | highBits | otherCnts;
}
if (chipset.majorVersion == 11) {
vmcnt = std::min(63u, vmcnt);
expcnt = std::min(7u, expcnt);
lgkmcnt = std::min(63u, lgkmcnt);
return (vmcnt << 10) | expcnt | (lgkmcnt << 4);
}
return failure();
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gfx12 has an entirely different system, yes? Should we support that here, or somewhere else?

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Yes, it uses different instructions and I not very familiar with. So, the high level questions: can amdgpu.waitcnt vmcnt(1) expcnt(2) lgkmcnt(3) format be semantically converted to these new instructions? Should we take more generic name for amdgpu wrapper, not referencing specific instruction? CC @kuhar

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From what I can tell, the gfx12 instructions are a more fine-grained version of pre-gfx12 ones, so that we can actually use the gfx12 categories and then combine them as needed for older architectures

But that feels like it could be future work.

(Though if you want to do it now, I might call it amdgpu.memory_counter_wait and give it loads, ds, store, sample, exp, and so on, following gfx12 and then packing into the relevant fields of s_waitcnt as needed

}

struct MemoryCounterWaitOpLowering
: public ConvertOpToLLVMPattern<MemoryCounterWaitOp> {
MemoryCounterWaitOpLowering(const LLVMTypeConverter &converter,
Chipset chipset)
: ConvertOpToLLVMPattern<MemoryCounterWaitOp>(converter),
chipset(chipset) {}

Chipset chipset;

LogicalResult
matchAndRewrite(MemoryCounterWaitOp op, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
if (chipset.majorVersion >= 12) {
Location loc = op.getLoc();
if (std::optional<int> ds = adaptor.getDs())
rewriter.create<ROCDL::WaitDscntOp>(loc, *ds);

if (std::optional<int> load = adaptor.getLoad())
rewriter.create<ROCDL::WaitLoadcntOp>(loc, *load);

if (std::optional<int> store = adaptor.getStore())
rewriter.create<ROCDL::WaitStorecntOp>(loc, *store);

if (std::optional<int> exp = adaptor.getExp())
rewriter.create<ROCDL::WaitExpcntOp>(loc, *exp);

rewriter.eraseOp(op);
return success();
}

auto getVal = [](Attribute attr) -> unsigned {
if (attr)
return cast<IntegerAttr>(attr).getInt();

// This value will be clamped to the maximum value for the chipset.
return 1024;
};
unsigned ds = getVal(adaptor.getDsAttr());
unsigned exp = getVal(adaptor.getExpAttr());

unsigned vmcnt = 1024;
Attribute load = adaptor.getLoadAttr();
Attribute store = adaptor.getStoreAttr();
if (load && store) {
vmcnt = getVal(load) + getVal(store);
} else if (load) {
vmcnt = getVal(load);
} else if (store) {
vmcnt = getVal(store);
}

FailureOr<unsigned> waitcnt = encodeWaitcnt(chipset, vmcnt, exp, ds);
if (failed(waitcnt))
return op.emitOpError("unsupported chipset");

rewriter.replaceOpWithNewOp<ROCDL::SWaitcntOp>(op, *waitcnt);
return success();
}
};

struct LDSBarrierOpLowering : public ConvertOpToLLVMPattern<LDSBarrierOp> {
LDSBarrierOpLowering(const LLVMTypeConverter &converter, Chipset chipset)
: ConvertOpToLLVMPattern<LDSBarrierOp>(converter), chipset(chipset) {}
Expand Down Expand Up @@ -1825,9 +1931,9 @@ void mlir::populateAMDGPUToROCDLConversionPatterns(LLVMTypeConverter &converter,
ROCDL::RawPtrBufferAtomicUminOp>,
RawBufferOpLowering<RawBufferAtomicCmpswapOp,
ROCDL::RawPtrBufferAtomicCmpSwap>,
AMDGPUDPPLowering, LDSBarrierOpLowering, SchedBarrierOpLowering,
MFMAOpLowering, ScaledMFMAOpLowering, WMMAOpLowering,
ExtPackedFp8OpLowering, ScaledExtPackedOpLowering,
AMDGPUDPPLowering, MemoryCounterWaitOpLowering, LDSBarrierOpLowering,
SchedBarrierOpLowering, MFMAOpLowering, ScaledMFMAOpLowering,
WMMAOpLowering, ExtPackedFp8OpLowering, ScaledExtPackedOpLowering,
PackedScaledTruncOpLowering, PackedTrunc2xFp8OpLowering,
PackedStochRoundFp8OpLowering, GatherToLDSOpLowering,
TransposeLoadOpLowering>(converter, chipset);
Expand Down
42 changes: 42 additions & 0 deletions mlir/test/Conversion/AMDGPUToROCDL/memory_counter_wait.mlir
Original file line number Diff line number Diff line change
@@ -0,0 +1,42 @@
// RUN: mlir-opt %s -convert-amdgpu-to-rocdl=chipset=gfx942 | FileCheck %s --check-prefixes=CHECK,GFX9
// RUN: mlir-opt %s -convert-amdgpu-to-rocdl=chipset=gfx1030 | FileCheck %s --check-prefixes=CHECK,GFX10
// RUN: mlir-opt %s -convert-amdgpu-to-rocdl=chipset=gfx1100 | FileCheck %s --check-prefixes=CHECK,GFX11
// RUN: mlir-opt %s -convert-amdgpu-to-rocdl=chipset=gfx1201 | FileCheck %s --check-prefixes=CHECK,GFX12

// CHECK-LABEL: func @memory_counter_wait
func.func @memory_counter_wait() {
// GFX9: rocdl.s.waitcnt 53119
// GFX10: rocdl.s.waitcnt 65407
// GFX11: rocdl.s.waitcnt 65527
// GFX12-NOT: rocdl.s.wait.loadcnt
// GFX12-NOT: rocdl.s.wait.storecnt
// GFX12-NOT: rocdl.s.wait.expcnt
// GFX12-NOT: rocdl.s.wait.dscnt
amdgpu.memory_counter_wait

// GFX9: rocdl.s.waitcnt 3952
// GFX10: rocdl.s.waitcnt 16240
// GFX11: rocdl.s.waitcnt 1015
// GFX12: rocdl.s.wait.loadcnt 0
amdgpu.memory_counter_wait load(0)

// GFX9: rocdl.s.waitcnt 3952
// GFX10: rocdl.s.waitcnt 16240
// GFX11: rocdl.s.waitcnt 1015
// GFX12: rocdl.s.wait.storecnt 0
amdgpu.memory_counter_wait store(0)

// GFX9: rocdl.s.waitcnt 53007
// GFX10: rocdl.s.waitcnt 65295
// GFX11: rocdl.s.waitcnt 65520
// GFX12: rocdl.s.wait.expcnt 0
amdgpu.memory_counter_wait exp(0)

// GFX9: rocdl.s.waitcnt 49279
// GFX10: rocdl.s.waitcnt 49279
// GFX11: rocdl.s.waitcnt 64519
// GFX12: rocdl.s.wait.dscnt 0
amdgpu.memory_counter_wait ds(0)

return
}
17 changes: 17 additions & 0 deletions mlir/test/Dialect/AMDGPU/ops.mlir
Original file line number Diff line number Diff line change
Expand Up @@ -548,3 +548,20 @@ func.func @gather_to_lds(%idx1 : index, %idx2 : index, %mem1 : memref<32xf16>, %
amdgpu.gather_to_lds %mem1[%idx1], %smem2[%idx1, %idx2] : vector<2xf16>, memref<32xf16>, memref<32x32xf16, #gpu.address_space<workgroup>>
func.return
}

// CHECK-LABEL: func @memory_counter_wait
func.func @memory_counter_wait() {
// CHECK: amdgpu.memory_counter_wait load(1) store(2) ds(3) exp(4)
// CHECK: amdgpu.memory_counter_wait load(4) store(2) ds(3) exp(1)
// CHECK: amdgpu.memory_counter_wait load(1)
// CHECK: amdgpu.memory_counter_wait store(2)
// CHECK: amdgpu.memory_counter_wait ds(3)
// CHECK: amdgpu.memory_counter_wait exp(4)
amdgpu.memory_counter_wait load(1) store(2) ds(3) exp(4)
amdgpu.memory_counter_wait exp(1) store(2) ds(3) load(4)
amdgpu.memory_counter_wait load(1)
amdgpu.memory_counter_wait store(2)
amdgpu.memory_counter_wait ds(3)
amdgpu.memory_counter_wait exp(4)
func.return
}