[ARM CPU] SVE support for Sgemm kernel #26027

akote123 · 2025-09-12T15:07:31Z

This PR ports the SGEMM kernel and associated packing kernels to the ARM SVE (Scalable Vector Extension) backend. Specifically, it introduces new wrapper implementations for SVE functions in lib/sve/sgemm_sve.cpp and integrates these wrappers within the existing kernel implementations.

Motivation and Context

This work is part of an ongoing effort to enhance ONNX Runtime's performance and architecture-awareness on ARM platforms. By leveraging ARM SVE, we aim to unlock better computational efficiency and scalability on modern ARM hardware.

This PR builds upon and extends the SVE work introduced in PR #25238

Performance Analysis:

Results are captured from sve 256,128 and SVE 512 supported machines.
This PR is a joint contribution by:

Aruna K(@akote123)
Nikhil R Sharma(@nikhilfujitsu)

akote123 · 2025-09-12T15:08:26Z

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akote123 · 2025-09-16T04:53:21Z

CC: @edgchen1 , @hariharans29

Code rebase

code rebase Code update code cleanup code cleanup cleanup Cleanup Cleanup

hariharans29 · 2025-09-30T03:20:34Z

Please address the build failures and please run onnxruntime_mlas_test in your env with your change and report any failures if any here.

akote123 · 2025-09-30T09:01:27Z

onnxruntime_mlas_test
@hariharans29 ,
Thank you. I have fixed CI failures and tested onxruntime_mlas_test in gr3, with #26203 fix all tests are passing

hariharans29 · 2025-09-30T16:24:50Z

/azp run Linux QNN CI Pipeline, Win_TRT_Minimal_CUDA_Test_CI, Windows ARM64 QNN CI Pipeline, Windows GPU Doc Gen CI Pipeline, Windows x64 QNN CI Pipeline

azure-pipelines · 2025-09-30T16:25:12Z

Azure Pipelines successfully started running 4 pipeline(s).

hariharans29 · 2025-10-01T01:01:29Z

cmake/CMakeLists.txt

 if(TARGET onnxruntime_providers)
  include("${CMAKE_CURRENT_SOURCE_DIR}/onnxruntime_providers_pch.cmake")
-endif()
+endif()


Nit: Stale change

hariharans29 · 2025-10-01T01:01:35Z

onnxruntime/core/mlas/lib/mlasi.h


    bool HasArmNeon_BF16() const { return has_arm_neon_bf16_; }
-
+    


Nit: Stale change

hariharans29 · 2025-10-01T01:08:00Z

onnxruntime/core/mlas/lib/sgemm.cpp


+                    SVE_LOAD_STORE(D,b);
+
+                    D += 16;


Is the mixed usage of the macro MLAS_SGEMM_STRIDEN_THREAD_ALIGN and hard-coded value of 16 intentional ? Can we just go back to the earlier usage of 16 in the while condition ?

we can go back to usage of 16 in while condition . Will update same.

hariharans29 · 2025-10-01T01:09:23Z

onnxruntime/core/mlas/lib/sgemm.cpp

+#if defined(MLAS_USE_SVE) || defined(MLAS_NEON_INTRINSICS)
+    if(MLAS_CPUIDINFO::GetCPUIDInfo().HasArmSve())
+    {
+#if defined(MLAS_USE_SVE)   


I feel there is something wrong in the code/design here - what happens when MLAS_USE_SVE is false and MLAS_NEON_INTRINSICS is true and HasArmSve() evaluates to true ?

HasArmSve() is added to address runtime check for SVE , will update the code to handle above condition properly

hariharans29 · 2025-10-01T01:16:01Z

onnxruntime/core/mlas/lib/sgemm.cpp

-            vst4q_f32(D, vld4q_f32(b));
+        while (CountX >= MLAS_SGEMM_STRIDEN_THREAD_ALIGN) {
+
+        const float* b = B;


Isn't there a lot of overlap between the code here ? Can the duplication be avoided and the code here be better re-written so that the code only differs only on the store instruction ?

hariharans29 · 2025-10-01T01:17:56Z

onnxruntime/core/mlas/lib/sgemm.cpp

            const float* b = B;
-
+#if defined(MLAS_USE_SVE) || defined(MLAS_NEON_INTRINSICS)
+    if (MLAS_CPUIDINFO::GetCPUIDInfo().HasArmSve()) {


Same comment as before - what happens when MLAS_USE_SVE is false and MLAS_NEON_INTRINSICS is true and HasArmSve() evaluates to true ?

hariharans29 · 2025-10-01T01:19:53Z

onnxruntime/core/mlas/lib/sve/mlasi_sve.h

+void MLAS_SVE_TARGET MLASCALL
+SCATTER_STORE(float* d, const float* b);
+
+void MLAS_SVE_TARGET


All the files have formatting issues. Can you please address them ?

hariharans29 · 2025-10-01T04:10:21Z

Have you tried this on multiple Gemm problem shapes - Please submit comprehensive micro-benchmarks for all SVE platforms.

I tried taking this change on a Graviton4 and for a Conv heavy model (which uses Im2Col + SGemm for the Conv implementation), it slows down the model very much - when I build with --no_sve, the perf is fine again. So, it seems like this Gemm implementation is not performant for all Gemm shapes yet.

akote123 · 2025-10-01T08:08:19Z

Have you tried this on multiple Gemm problem shapes - Please submit comprehensive micro-benchmarks for all SVE platforms.

I tried taking this change on a Graviton4 and for a Conv heavy model (which uses Im2Col + SGemm for the Conv implementation), it slows down the model very much - when I build with --no_sve, the perf is fine again. So, it seems like this Gemm implementation is not performant for all Gemm shapes yet.

Yes. I have tried on different shapes ,and for large shapes tuning is required. This PR is added as patch to enable sve for gemm kernel and for larger shapes this gemm implementation has to be tuned and we are currently working on that.

hariharans29 · 2025-11-18T03:39:57Z

Hi @akote123: Any plan to resume this work ? Or at the very least, can you please guide what remains to be done for perf tuning ?

akote123 · 2025-11-18T04:59:28Z

@hariharans29 ,Thank you. We will resume this work .This PR we planned as SVE sgemm enablement work and do performance tuning as future task and contribute

akote123 force-pushed the aruna/sgemm_sve branch from 7ebfed8 to ff2a6a4 Compare September 15, 2025 08:19

akote123 changed the title ~~[DRAFT][ARM CPU] SVE support for Sgemm kernel~~ [ARM CPU] SVE support for Sgemm kernel Sep 15, 2025

ADD support for SVE sgemm

d762023

Code rebase

akote123 force-pushed the aruna/sgemm_sve branch from acf16b6 to 2493ad2 Compare September 23, 2025 10:14

akote123 added 2 commits September 23, 2025 16:49

Updates to fix issue in Gr2

de79d1a

code rebase Code update code cleanup code cleanup cleanup Cleanup Cleanup

Cleanup

c508e83

akote123 force-pushed the aruna/sgemm_sve branch from 8e968e8 to c508e83 Compare September 23, 2025 11:20

akote123 added 2 commits September 24, 2025 14:27

Fix Compilation errors

d997270

Fix Accuracy Errors

5dd2161

akote123 force-pushed the aruna/sgemm_sve branch from 6ee2ffc to 5dd2161 Compare September 24, 2025 08:57

Fix CI Failure

11f7267

hariharans29 reviewed Oct 1, 2025

View reviewed changes

onnxruntime/core/mlas/lib/mlasi.h Outdated

bool HasArmNeon_BF16() const { return has_arm_neon_bf16_; }

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Nit: Stale change

hariharans29 reviewed Oct 1, 2025

View reviewed changes

akote123 added 2 commits November 18, 2025 14:43

Code formating

9729a1a

Update

f12f872

Merge branch 'main' into aruna/sgemm_sve

0699ab8

akote123 force-pushed the aruna/sgemm_sve branch from 903f766 to 7f3180f Compare November 18, 2025 10:29

akote123 added 2 commits November 18, 2025 16:00

code formating

db2bfe9

code formating

2e2c6db

akote123 force-pushed the aruna/sgemm_sve branch from 7f3180f to 2e2c6db Compare November 18, 2025 10:30

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