[pull] main from llvm:main #648
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…#165922) Test float/double/half/bfloat on RISC-V without F extension.
…ming scalar (#165800) Baseline test for #165793 exposing the change from a vector fp-to-int conversion into a scalar one inside the loop. Additionally, removed `llvm/test/Transforms/InstCombine/vec_extract_var_elt-inseltpoison.ll`, which was a duplicate of `llvm/test/Transforms/InstCombine/vec_extract_var_elt.ll` differing only by the use of poison in the insert element. The poison variant has been merged into `llvm/test/Transforms/InstCombine/vec_extract_var_elt.ll`. Also improved test naming and updated test checks.
Previously, any blank lines in IR were ignored by UTC, leading to more fragile `CHECK`s being generated. This change lets UTC, 1) emit `CHECK-EMPTY` to check blank lines, and 2) generate more `CHECK-NEXT`s, landing the discussion #165419 (comment). Moreover, this change also aligns the behavior of IR check-gen to ASM check-gen, which has been emitting `CHECK-EMPTY` since a8a89c7.
… ones for each vector elements (#165980)
Some tests are failing on the build bots because of test environment/setup issues rather than code logic in PR #165360. As a temporary workaround, these tests are being disabled to allow the rest of the build to pass. Once the test setup is fixed, the tests will be re-enabled. https://lab.llvm.org/buildbot/#/builders/180/builds/27660. https://lab.llvm.org/buildbot/#/builders/160/builds/27520.
For blocks with multiple predescessors, there maybe `SMEM` and `VMEM` events active at the same time. This patch handles these cases.
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