COPIFT Queues

.dockerignore

@@ -1,4 +1,5 @@
 *
 !sw/**/*.py
 !util/**/*.py
+!target/snitch_cluster/util/*.py
 !pyproject.toml

.github/workflows/ci.yml

@@ -39,7 +39,7 @@ jobs:
           cache-to: type=gha,mode=max`
           file: util/container/Dockerfile
           push: true
-          tags: ghcr.io/pulp-platform/snitch_cluster:${{ github.ref_name }}
+          tags: ghcr.io/${{ github.repository_owner }}/snitch_cluster:${{ github.ref_name }}
 
   ########
   # Docs #
@@ -53,7 +53,7 @@ jobs:
       github.event_name != 'pull_request' ||
       github.event.pull_request.head.repo.full_name != github.repository
     container:
-      image: ghcr.io/pulp-platform/snitch_cluster:${{ github.ref_name }}
+      image: ghcr.io/${{ github.repository_owner }}/snitch_cluster:${{ github.ref_name }}
     steps:
       - uses: actions/checkout@v2
       - name: Build docs
@@ -71,7 +71,7 @@ jobs:
       github.event_name != 'pull_request' ||
       github.event.pull_request.head.repo.full_name != github.repository
     container:
-      image: ghcr.io/pulp-platform/snitch_cluster:${{ github.ref_name }}
+      image: ghcr.io/${{ github.repository_owner }}/snitch_cluster:${{ github.ref_name }}
     steps:
       - uses: actions/checkout@v2
       - name: Run pytest
@@ -89,7 +89,7 @@ jobs:
       github.event_name != 'pull_request' ||
       github.event.pull_request.head.repo.full_name != github.repository
     container:
-      image: ghcr.io/pulp-platform/snitch_cluster:${{ github.ref_name }}
+      image: ghcr.io/${{ github.repository_owner }}/snitch_cluster:${{ github.ref_name }}
     steps:
       - uses: actions/checkout@v2
         with:
@@ -140,7 +140,7 @@ jobs:
   #     github.event_name != 'pull_request' ||
   #     github.event.pull_request.head.repo.full_name != github.repository
   #   container:
-  #     image: ghcr.io/pulp-platform/snitch_cluster:${{ github.ref_name }}
+  #     image: ghcr.io/${{ github.repository_owner }}/snitch_cluster:${{ github.ref_name }}
   #   steps:
   #     - uses: actions/checkout@v2
   #       with:
@@ -167,7 +167,7 @@ jobs:
       github.event_name != 'pull_request' ||
       github.event.pull_request.head.repo.full_name != github.repository
     container:
-      image: ghcr.io/pulp-platform/snitch_cluster:${{ github.ref_name }}
+      image: ghcr.io/${{ github.repository_owner }}/snitch_cluster:${{ github.ref_name }}
     steps:
       - uses: actions/checkout@v4
         with:

Bender.lock

@@ -7,8 +7,8 @@ packages:
     dependencies:
     - common_cells
   axi:
-    revision: 4e54ac6766b160217a83a74d5a23af9bbf59e6ee
-    version: null
+    revision: 853ede23b2a9837951b74dbdc6d18c3eef5bac7d
+    version: 0.39.5
     source:
       Git: https://github.com/pulp-platform/axi
     dependencies:
@@ -32,8 +32,8 @@ packages:
     dependencies:
     - common_cells
   cluster_icache:
-    revision: 0e1fb6751d9684d968ba7fb40836e6118b448ecd
-    version: 0.1.1
+    revision: 64e21ae455bbdde850c4df13bef86ea55ac42537
+    version: null
     source:
       Git: https://github.com/pulp-platform/cluster_icache.git
     dependencies:
@@ -42,8 +42,8 @@ packages:
     - scm
     - tech_cells_generic
   common_cells:
-    revision: c27bce39ebb2e6bae52f60960814a2afca7bd4cb
-    version: 1.37.0
+    revision: 842753eabe166818bde831908c865872d115528d
+    version: null
     source:
       Git: https://github.com/pulp-platform/common_cells
     dependencies:
@@ -91,8 +91,8 @@ packages:
     - common_cells
     - common_verification
   register_interface:
-    revision: ae616e5a1ec2b41e72d200e5ab09c65e94aebd3d
-    version: 0.4.4
+    revision: 5daa85d164cf6b54ad061ea1e4c6f3624556e467
+    version: 0.4.5
     source:
       Git: https://github.com/pulp-platform/register_interface
     dependencies:

Bender.yml

@@ -19,14 +19,14 @@ package:
     - Matheus Cavalcante <[email protected]>
 
 dependencies:
-  axi:                { git: https://github.com/pulp-platform/axi,                rev:  4e54ac6766b160217a83a74d5a23af9bbf59e6ee  }
-  axi_riscv_atomics:  { git: https://github.com/pulp-platform/axi_riscv_atomics,  version:  0.6.0   }
-  common_cells:       { git: https://github.com/pulp-platform/common_cells,       version:  1.35.0  }
-  FPnew:              { git: "https://github.com/pulp-platform/cvfpu.git",        rev:      pulp-v0.1.3 }
-  register_interface: { git: https://github.com/pulp-platform/register_interface, version:  0.4.2   }
-  tech_cells_generic: { git: https://github.com/pulp-platform/tech_cells_generic, version:  0.2.11  }
-  riscv-dbg:          { git: https://github.com/pulp-platform/riscv-dbg,          version:  0.8.0   }
-  cluster_icache:     { git: https://github.com/pulp-platform/cluster_icache.git, version:  0.1.0   }
+  axi:                { git: https://github.com/pulp-platform/axi,                version: 0.39.5  }
+  axi_riscv_atomics:  { git: https://github.com/pulp-platform/axi_riscv_atomics,  version: 0.6.0   }
+  common_cells:       { git: https://github.com/pulp-platform/common_cells,       rev:     remove-ffnr }
+  FPnew:              { git: https://github.com/pulp-platform/cvfpu.git,          rev:     pulp-v0.1.3 }
+  register_interface: { git: https://github.com/pulp-platform/register_interface, version: 0.4.2   }
+  tech_cells_generic: { git: https://github.com/pulp-platform/tech_cells_generic, version: 0.2.11  }
+  riscv-dbg:          { git: https://github.com/pulp-platform/riscv-dbg,          version: 0.8.0   }
+  cluster_icache:     { git: https://github.com/pulp-platform/cluster_icache.git, rev:     64e21ae455bbdde850c4df13bef86ea55ac42537 }
   idma:               { git: https://github.com/pulp-platform/iDMA,               rev: __deploy__9cbcd30__snitch-tracing }
 
 export_include_dirs:
@@ -35,6 +35,7 @@ export_include_dirs:
   - hw/tcdm_interface/include
   - hw/snitch/include
   - hw/snitch_ssr/include
+  - target/snitch_cluster/generated
 
 sources:
   # reqrsp_interface
@@ -93,6 +94,8 @@ sources:
       # Level 0
       - hw/snitch/src/snitch_pma_pkg.sv
       - hw/snitch/src/riscv_instr.sv
+      - hw/snitch/src/snitch_fp_queue.sv
+      - hw/snitch/src/snitch_in_queue.sv
       # Level 1
       - hw/snitch/src/snitch_pkg.sv
       # Level 2
@@ -116,14 +119,14 @@ sources:
   - files:
       - hw/snitch_vm/src/snitch_ptw.sv
 
-  # snitch_ipu
-  - files:
-      # Level 0
-      - hw/snitch_ipu/src/snitch_ipu_pkg.sv
-      # Level 1
-      - hw/snitch_ipu/src/snitch_ipu_alu.sv
-      # Level 2
-      - hw/snitch_ipu/src/snitch_int_ss.sv
+  # # snitch_ipu
+  # - files:
+  #     # Level 0
+  #     - hw/snitch_ipu/src/snitch_ipu_pkg.sv
+  #     # Level 1
+  #     - hw/snitch_ipu/src/snitch_ipu_alu.sv
+  #     # Level 2
+  #     - hw/snitch_ipu/src/snitch_int_ss.sv
 
   # snitch_ssr
   - files:
@@ -185,8 +188,19 @@ sources:
 
   # target/snitch_cluster
   - target: snitch_cluster
+    files:
+      - target/snitch_cluster/generated/snitch_cluster_pkg.sv
+  - target: all(snitch_cluster, not(postlayout))
     files:
       - target/snitch_cluster/generated/snitch_cluster_wrapper.sv
+  - target: all(snitch_cluster, postlayout)
+    files:
+      - nonfree/gf12/fusion/runs/0/out/15/snitch_cluster_wrapper.v
   - target: all(snitch_cluster, any(simulation, verilator))
     files:
       - target/snitch_cluster/test/testharness.sv
+
+  - target: gf12
+    files:
+      - nonfree/gf12/mems/tc_sram.sv
+      - nonfree/gf12/sourcecode/tc_clk.sv

Makefile

@@ -27,7 +27,7 @@ ROOT = $(dir $(abspath $(lastword $(MAKEFILE_LIST))))
 ############
 
 NONFREE_REMOTE ?= [email protected]:pulp-restricted/snitch-cluster-nonfree.git
-NONFREE_COMMIT ?= e30961e20a23a76442da27d2ba07c9fe20f3b575
+NONFREE_COMMIT ?= synth
 NONFREE_DIR = $(ROOT)/nonfree
 
 all: nonfree

docs/ug/trace_analysis.md

@@ -128,6 +128,7 @@ In the following table you can find a complete list of all the performance metri
 |`snitch_issues`           |Total number of instructions issued by Snitch, excluding those offloaded to the FPSS (see `snitch_fseq_offloads`).                                                                                  |
 |`snitch_fseq_offloads`    |Total number of instructions offloaded by Snitch to the FPSS.                                                                                                                                       |
 |`snitch_fseq_rel_offloads`|The ratio between `snitch_fseq_offloads` and the total number of instructions issued by Snitch core proper, i.e. `snitch_issues + snitch_fseq_offloads`.                                            |
+|`snitch_occupancy`        |IPC of the Snitch core, calculated as `snitch_issues / cycles`.                                                                                                                                     |
 |`fpss_issues`             |Total number of instructions issued by the FPSS. It counts repeated issues from the FREP sequencer.                                                                                                 |
 |`fpss_fpu_issues`         |Similar to `fpss_issues`, but counts only instructions destined to the FPU proper. It does not for instance include instructions issued to the FPSS's LSU.                                          |
 |`fseq_yield`              |The ratio between `fpss_issues` and `snitch_fseq_offloads`. The difference lies in the FREP sequencer possibly replicating instructions. If the sequencer is not used this ratio should amount to 1.|

docs/ug/tutorial.md

@@ -149,7 +149,7 @@ bin/snitch_cluster.vsim.gui sw/apps/blas/axpy/build/axpy.elf
 
 ## Debugging and benchmarking
 
-When you run a simulation, every core logs all the instructions it executes in a trace file. The traces are located in the `logs` folder within the simulation directory. Every trace is identified by a hart ID, that is a unique ID for every _hardware thread (hart)_ in a RISC-V system (and since all our cores have a single thread that is a unique ID per core).
+When you run a simulation, every core logs all the instructions it executes in a trace file. The traces are located in the `logs` folder within the _simulation directory_. Every trace is identified by a hart ID, that is a unique ID for every _hardware thread (hart)_ in a RISC-V system (and since all our cores have a single thread that is a unique ID per core).
 
 The simulation dumps the traces in a non-human-readable format with `.dasm` extension. To convert these to a human-readable form run:
 
@@ -345,3 +345,95 @@ As you may have noticed, there is a good deal of code which is independent of th
 It is thus preferable to develop the data generation scripts and Snitch kernels in a shared location, from which multiple platforms can take and include the code. The `sw` directory in the root of this repository was created with this goal in mind. For the AXPY example, shared sources are hosted under the `sw/blas/axpy` directory.
 
 We recommend that you follow this approach also in your own developments for as much of the code which can be reused.
+
+## Implementing the hardware
+
+If you make changes to the hardware, you probably also want to physically implement it to estimate the PPA impact of your modifications. As the physical implementation flow involves proprietary tools licensed under non-disclosure agreements, our physical implementation flow is contained in a separate private git repository. If you are an IIS user, with access to our Gitlab server and IIS machines, you may follow the next instructions to replicate our implementation flow.
+
+Firstly, we need to clone all the sources for the physical flow. The following command takes care of everything for you:
+```shell
+make nonfree
+```
+
+Behind the scenes, it will clone the `snitch-cluster-nonfree` repo under the `nonfree` folder. Let's move into this folder:
+
+```shell
+cd nonfree
+```
+
+Here, you will find a Makefile with a series of convenience targets to launch our flow up to a certain stage: may it be elaboration (`elab`), synthesis (`synth`) or place-and-route (`pnr`). If you can wait long enough you may also launch the entire flow to produce a final optimized post-layout netlist:
+
+```shell
+make post-layout-netlist
+```
+
+This may take as long as a day, or more, depending on your machine's performance. If you previously launched the flow up to a certain stage, you can resume it from that point without restarting from scratch. Just specify the `FIRST_STAGE` flag with the name of the stage you want to start from, e.g.:
+
+```shell
+make FIRST_STAGE=synth-init-opto post-layout-netlist
+```
+
+You will find reports and output files produced by the flow in the `nonfree/gf12/fusion/runs/0/` folder, respectively in the `reports` and `out` subdirectories, separated into individual subdirectories for every stage in the flow. These are all you should need to derive area and timing numbers for your design.
+
+## Running a physical simulation
+
+Once your design is physically implemented, you want to also verify that it works as intended.
+Assuming you used the previous command to get a final optimized post-layout netlist, you can directly build a simulation model out of it. Head back to the main repository, in the `target/snitch_cluster` folder, and build the simulation model with the following flag:
+
+```shell
+<<<<<<< HEAD
+make clean-vsim
+=======
+>>>>>>> eeefc1a... treewide: Add post-layout simulation flow
+make PL_SIM=1 bin/snitch_cluster.vsim
+```
+
+This resembles the commands you've previously seen in section [Building the hardware](#building-the-hardware). In fact, all testbench components are the same, we simply use the added flag to tell [Bender](https://github.com/pulp-platform/bender) to reference the physical netlist in place of the source RTL as a DUT during compilation.
+The `Bender.yml` file in the root of the repository automatically references the final netlist in our flow, but you could replace that with a netlist from an intermediate stage if you do not intend to run the whole flow.
+
+<<<<<<< HEAD
+!!! note
+    Make is not aware of the effect of this flag, so it will not update the RTL source list for compilation. To ensure that it is updated, we can delete the compilation script, which was implicitly generated when you last built the simulation model. The first command above achieves this, by deleting all artifacts from the last build.
+
+=======
+>>>>>>> eeefc1a... treewide: Add post-layout simulation flow
+Running a physical simulation is then no different from running a functional simulation, so you may continue using the commands introduced in section [Running a simulation](#running-a-simulation).
+
+## Power estimation
+
+During physical implementation, the tools are able to independently generate area and timing numbers. For a complete PPA analysis, you will want to include power estimates as well.
+
+Power numbers are extremely dependent on the switching activity in your circuit, which in turn depends on the stimuli you intend to feed in to your DUT, so you are in charge of providing this information to the tools. The switching activity is typically recorded in the form of a [VCD](https://en.wikipedia.org/wiki/Value_change_dump) file, and can be generated by most RTL simulators.
+
+To do so, set the `VCD_DUMP` flag when building the physical simulation model:
+```shell
+make PL_SIM=1 VCD_DUMP=1 DEBUG=ON bin/snitch_cluster.vsim
+``` 
+
+!!! danger
+    When using QuestaSim for VCD generation, you must build the model with the `DEBUG=ON` flag, to ensure that all nets are preserved during compilation, preventing them from being optimized away. This guarantees that the VCD file contains switching activity for all nets in your circuit. 
+
+When you run a simulation, the simulator will now automatically create a `vcd` subdirectory within the _simulation directory_, where a VCD file is generated.
+
+Most often you are not interested in estimating the power of an entire simulation, but only of a specific section, e.g. a kernel execution.
+You can pass start and end times for VCD recording to the simulation as environment variables:
+
+```shell
+VCD_START=127ns VCD_END=8898ns bin/snitch_cluster.vsim sw/apps/blas/axpy/build/axpy.elf
+```
+
+!!! note
+    Variable assignments must preceed the executable in a shell command to be interpreted as environment variable assignments. Note that environment variables set this way only persist for the current command.
+
+A benefit of RTL simulations is that they are cycle-accurate. You can thus use them as a reference to find the start and end times of interest with the help of the simulation traces (unavailable during physical simulation), and directly apply these to the physical simulation.
+
+With a VCD file at your disposal, you can now estimate the power consumption of your circuit. In the non-free repository, run the following command:
+```shell
+make SIM_DIR=<path_to_simulation_directory> power
+```
+You need to point the command to the _simulation directory_ in which the VCD dump was generated, for it to find the VCD file.
+
+!!! note
+    Since the actual simulation command is run in a different directory, you need to point to the _simulation directory_ using an absolute path.
+
+Once the command terminates, you will find power reports in the `nonfree/gf12/synopsys/reports` folder, from which you can extract relevant power numbers.