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18cc32b
(fix) added cls pointer init
Jul 4, 2025
14e3791
(feat) HW support for narrow reduction
Jun 16, 2025
35e16bd
(feat) SW support for narrow reduction
Jun 18, 2025
7f687fe
(feat) HW support for wide reduction
Jun 16, 2025
69de9ce
(feat) SW support for wide reduction
Jul 4, 2025
a7bc2ec
(feat) fix all configurations to account for the features
Jul 4, 2025
1429a97
(feat) introduce memory fences in the syncronization methodes
Jul 9, 2025
5d112e9
(misc)
Jul 9, 2025
45e9399
Add USER CSRs and DMUSER instruction to riscv-opcodes
colluca Jul 10, 2025
0a3cde5
hw: Add user field to rspreq interface
colluca Jul 10, 2025
50e0eeb
hw: Parameterize Snitch LSU user width
colluca Jul 10, 2025
7278e2b
hw: Undo change in narrow XBAR's port index order
colluca Jul 10, 2025
f9811d7
sw: Fix fence in start.c routine
colluca Jul 10, 2025
515c3f2
hw: Reuse default port configuration for both unicast and multicast X…
colluca Jul 10, 2025
29836da
hw: Make `select_t` an enum for readability and clean comment
colluca Jul 10, 2025
a922c02
hw: Follow generate block label naming convention
colluca Jul 10, 2025
a2fc663
hw: Rename user fields and make code less verbose
colluca Jul 10, 2025
60a8d6e
sw: Improve narrow collectives API
colluca Jul 10, 2025
2ebb241
sw: Improve wide collectives API
colluca Jul 10, 2025
280bea7
hw: Derive *UserWidth parameters from user_*_t parameters
colluca Jul 10, 2025
c7550c0
treewide: Remove reroute parameter and rename enable_multicast parame…
colluca Jul 10, 2025
c105f74
hw: Fix compilation errors
colluca Jul 10, 2025
2d335b3
sw: Fix compilation errors
colluca Jul 10, 2025
f24633f
hw: Clean up collective connectivity matrices
colluca Jul 11, 2025
d35f6d0
sw: Fix linting errors
colluca Jul 11, 2025
7081573
bender: Bump AXI
colluca Jul 11, 2025
d6686f6
hw: Update reqrsp and TCDM interface testbenches
colluca Jul 11, 2025
00f96fb
iis-setup.sh: Fix oseda container version
colluca Jul 11, 2025
b9d0774
hw: Fix errors related to select_t type
colluca Jul 11, 2025
976282f
hw: Fix port mismatch errors
colluca Jul 11, 2025
fb1342b
treewide: Replace legacy parameters with enable_*_collectives parameters
colluca Jul 11, 2025
52d09c3
cfg: Disable collectives as this requires loopback from SoC
colluca Jul 11, 2025
d67396a
sw: Revert `snrt_inter_cluster_barrier` to work for other than DMA cores
colluca Jul 11, 2025
0741e9a
sw: Add comment in `multi_cluster` test
colluca Jul 11, 2025
6a7e9af
hw: Remove external memory from multicast rules
colluca Jul 15, 2025
d651676
treewide: Add `reduction_opcode_width` configuration parameter
colluca Jul 15, 2025
9459607
(feat) Add external DCA (direct compute access) to the snitch cluster.
Jun 16, 2025
12d4178
Merge everything relevant to the GEMM / MHA from snitch into my brunch
Jul 25, 2025
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4 changes: 2 additions & 2 deletions Bender.lock
Original file line number Diff line number Diff line change
Expand Up @@ -7,10 +7,10 @@ packages:
dependencies:
- common_cells
axi:
revision: bec548fa2a9b18cbd7531105bb1fdf481ea8ad49
revision: 458c8c58cbe0acd0c5e6bb8592b52111bc9a5d84
version: null
source:
Git: https://github.com/colluca/axi.git
Git: https://github.com/Lura518/axi.git
dependencies:
- common_cells
- common_verification
Expand Down
2 changes: 1 addition & 1 deletion Bender.yml
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@ package:
- Matheus Cavalcante <[email protected]>

dependencies:
axi: { git: https://github.com/colluca/axi, rev: multicast }
axi: { git: https://github.com/Lura518/axi, rev: reduction }
axi_riscv_atomics: { git: https://github.com/pulp-platform/axi_riscv_atomics, version: 0.6.0 }
common_cells: { git: https://github.com/pulp-platform/common_cells, rev: snitch }
apb: { git: https://github.com/pulp-platform/apb.git, version: 0.2.2 }
Expand Down
51 changes: 51 additions & 0 deletions docs/ug/system_integration.md
Original file line number Diff line number Diff line change
@@ -0,0 +1,51 @@
# Integrating the Snitch cluster in an SoC

While this repository provides many IPs that can be reused independently, we suggest to integrate the Snitch cluster as a whole, that is the `snitch_cluster` module, in derived systems.

The `snitch_cluster` module is implemented in [snitch_cluster.sv](https://github.com/pulp-platform/{{ repo }}/blob/{{ branch }}/hw/snitch_cluster/src/snitch_cluster.sv).

## Configurability

A reference instantiation of the Snitch cluster can be found in the testbench used to test the cluster within this repository, see [testharness.sv](https://github.com/pulp-platform/{{ repo }}/blob/{{ branch }}/target/snitch_cluster/test/testharness.sv).

As you may note, we do not instantiate the `snitch_cluster` directly but a so-called `snitch_cluster_wrapper`, with a much simplified interface. All parameters of the `snitch_cluster` module are set within the wrapper.

The benefit of the wrapper is that it can be programmatically generated from a single source of truth, namely a JSON5 configuration file, from which the software hardware-abstraction layer (HAL), and all other sources dependent on the configuration within the repository, are also generated.

This way, if you want to modify the cluster configuration, you don't have to go and manually change it in multiple places (the RTL, the HAL, etc.), but only in the single-source-of-truth cluster configuration file. More information on the configuration file can be found in the [tutorial](tutorial.md#configuring-the-hardware).

We suggest that the same approach is used when integrating the Snitch cluster in an SoC. This allows you to easily test different configurations of the cluster inside your SoC.

## Integrating the RTL

We provide Make rules to generate the cluster wrapper and other RTL files. Include the following lines in a Makefile, to inherit Snitch's rules:
```Makefile
SN_ROOT = $(shell $(BENDER) path snitch_cluster)

include $(SN_ROOT)/target/common/common.mk
include $(SN_ROOT)/target/common/rtl.mk
```

!!! note
Snitch's Makefiles require `SN_ROOT` to be defined and to point to the root of the Snitch cluster repository. You can set this however you prefer, i.e. you don't have to use Bender if you manage your dependencies in a different way.

You can then use the `sn-rtl` and `sn-clean-rtl` targets to respectively build and clean all of Snitch's generated RTL sources.
<!-- TODO(colluca): In Picobello we explicitly use the $(SN_CLUSTER_WRAPPER) $(SN_CLUSTER_PKG) variables to build only the generated sources that depend on the cluster config. Find a common ground, probably define targets for only those files. -->

## Integrating the software

Similarly, Snitch comes with a collection of software tests and applications. These build on the functions provided by the Snitch runtime library, so they must be linked against an implementation of the latter. The runtime library abstracts away all the low-level characteristics of the system, allowing applications to be written in a mostly system-independent way, and to be portable to any multi-cluster Snitch-based system.
To this end, every system must implement a hardware abstraction layer (HAL) for the Snitch runtime, which the mentioned infrastructure builds on.

Given a path to the platform-specific HAL sources, you can reuse the Snitch cluster's Make rules to build the runtime, tests and applications for the target platform.
Include the following lines in a Makefile, to inherit Snitch's rules:

```Makefile
SN_RUNTIME_HAL_DIR = sw/runtime/hal

include $(SN_ROOT)/target/common/sw.mk
```

The included Makefile(s) can be customized to some extent by overriding some variables before the Makefile inclusion line.
For example by setting `SNRT_BUILD_APPS = OFF` none of the default Snitch applications will be built.
You can explicitly set the list of applications to be built via the `SNRT_APPS` variable, which can include additional system-dependent applications you may develop in the system repository. For further information on the available customization options you may want to take a look inside the recursively included Makefiles.
20 changes: 10 additions & 10 deletions hw/reqrsp_interface/include/reqrsp_interface/typedef.svh
Original file line number Diff line number Diff line change
Expand Up @@ -8,15 +8,15 @@
`ifndef REQRSP_INTERFACE_TYPEDEF_SVH_
`define REQRSP_INTERFACE_TYPEDEF_SVH_

`define REQRSP_TYPEDEF_REQ_CHAN_T(__req_chan_t, __addr_t, __data_t, __strb_t) \
`define REQRSP_TYPEDEF_REQ_CHAN_T(__req_chan_t, __addr_t, __data_t, __strb_t, __user_t) \
typedef struct packed { \
__addr_t addr; \
__addr_t mask; \
logic write; \
reqrsp_pkg::amo_op_e amo; \
__data_t data; \
__strb_t strb; \
reqrsp_pkg::size_t size; \
__addr_t addr; \
logic write; \
reqrsp_pkg::amo_op_e amo; \
__data_t data; \
__strb_t strb; \
__user_t user; \
reqrsp_pkg::size_t size; \
} __req_chan_t;

`define REQRSP_TYPEDEF_RSP_CHAN_T(__rsp_chan_t, __data_t) \
Expand All @@ -39,8 +39,8 @@
logic q_ready; \
} __rsp_t;

`define REQRSP_TYPEDEF_ALL(__name, __addr_t, __data_t, __strb_t) \
`REQRSP_TYPEDEF_REQ_CHAN_T(__name``_req_chan_t, __addr_t, __data_t, __strb_t) \
`define REQRSP_TYPEDEF_ALL(__name, __addr_t, __data_t, __strb_t, __user_t) \
`REQRSP_TYPEDEF_REQ_CHAN_T(__name``_req_chan_t, __addr_t, __data_t, __strb_t, __user_t) \
`REQRSP_TYPEDEF_RSP_CHAN_T(__name``_rsp_chan_t, __data_t) \
`REQRSP_TYPEDEF_REQ_T(__name``_req_t, __name``_req_chan_t) \
`REQRSP_TYPEDEF_RSP_T(__name``_rsp_t, __name``_rsp_chan_t)
Expand Down
2 changes: 1 addition & 1 deletion hw/reqrsp_interface/src/axi_to_reqrsp.sv
Original file line number Diff line number Diff line change
Expand Up @@ -448,7 +448,7 @@ module axi_to_reqrsp_intf #(
typedef logic [IdWidth-1:0] id_t;
typedef logic [UserWidth-1:0] user_t;

`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)

`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
Expand Down
11 changes: 9 additions & 2 deletions hw/reqrsp_interface/src/reqrsp_cut.sv
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,8 @@ module reqrsp_cut #(
parameter int unsigned AddrWidth = 0,
/// Data width of the interface.
parameter int unsigned DataWidth = 0,
/// User width of the interface.
parameter int unsigned UserWidth = 0,
/// Request type.
parameter type req_t = logic,
/// Response type.
Expand All @@ -32,8 +34,9 @@ module reqrsp_cut #(
typedef logic [AddrWidth-1:0] addr_t;
typedef logic [DataWidth-1:0] data_t;
typedef logic [DataWidth/8-1:0] strb_t;
typedef logic [UserWidth-1:0] user_t;

`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)

spill_register #(
.T (reqrsp_req_chan_t),
Expand Down Expand Up @@ -74,6 +77,8 @@ module reqrsp_cut_intf #(
parameter int unsigned AddrWidth = 0,
/// Data width of the interface.
parameter int unsigned DataWidth = 0,
/// User width of the interface.
parameter int unsigned UserWidth = 0,
/// Bypass request channel.
parameter bit BypassReq = 0,
/// Bypass Response channel.
Expand All @@ -88,15 +93,17 @@ module reqrsp_cut_intf #(
typedef logic [AddrWidth-1:0] addr_t;
typedef logic [DataWidth-1:0] data_t;
typedef logic [DataWidth/8-1:0] strb_t;
typedef logic [UserWidth-1:0] user_t;

`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)

reqrsp_req_t reqrsp_slv_req, reqrsp_mst_req;
reqrsp_rsp_t reqrsp_slv_rsp, reqrsp_mst_rsp;

reqrsp_cut #(
.AddrWidth (AddrWidth),
.DataWidth (DataWidth),
.UserWidth (UserWidth),
.req_t (reqrsp_req_t),
.rsp_t (reqrsp_rsp_t),
.BypassReq (BypassReq),
Expand Down
5 changes: 4 additions & 1 deletion hw/reqrsp_interface/src/reqrsp_demux.sv
Original file line number Diff line number Diff line change
Expand Up @@ -104,6 +104,8 @@ module reqrsp_demux_intf #(
parameter int unsigned AddrWidth = 0,
/// Data width of the interface.
parameter int unsigned DataWidth = 0,
/// User width of the interface.
parameter int unsigned UserWidth = 0,
/// Amount of outstanding responses. Determines the FIFO size.
parameter int unsigned RespDepth = 8,
// Dependent parameters, DO NOT OVERRIDE!
Expand All @@ -120,8 +122,9 @@ module reqrsp_demux_intf #(
typedef logic [AddrWidth-1:0] addr_t;
typedef logic [DataWidth-1:0] data_t;
typedef logic [DataWidth/8-1:0] strb_t;
typedef logic [UserWidth-1:0] user_t;

`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)

reqrsp_req_t reqrsp_slv_req;
reqrsp_rsp_t reqrsp_slv_rsp;
Expand Down
11 changes: 9 additions & 2 deletions hw/reqrsp_interface/src/reqrsp_iso.sv
Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,8 @@ module reqrsp_iso #(
parameter int unsigned AddrWidth = 0,
/// Data width of the interface.
parameter int unsigned DataWidth = 0,
/// User width of the interface.
parameter int unsigned UserWidth = 0,
/// Request type.
parameter type req_t = logic,
/// Response type.
Expand Down Expand Up @@ -43,8 +45,9 @@ module reqrsp_iso #(
typedef logic [AddrWidth-1:0] addr_t;
typedef logic [DataWidth-1:0] data_t;
typedef logic [DataWidth/8-1:0] strb_t;
typedef logic [UserWidth-1:0] user_t;

`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)

isochronous_spill_register #(
.T (reqrsp_req_chan_t),
Expand Down Expand Up @@ -89,6 +92,8 @@ module reqrsp_iso_intf #(
parameter int unsigned AddrWidth = 0,
/// Data width of the interface.
parameter int unsigned DataWidth = 0,
/// User width of the interface.
parameter int unsigned UserWidth = 0,
/// Bypass.
parameter bit BypassReq = 0,
parameter bit BypassRsp = 0
Expand All @@ -110,15 +115,17 @@ module reqrsp_iso_intf #(
typedef logic [AddrWidth-1:0] addr_t;
typedef logic [DataWidth-1:0] data_t;
typedef logic [DataWidth/8-1:0] strb_t;
typedef logic [UserWidth-1:0] user_t;

`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)

reqrsp_req_t reqrsp_src_req, reqrsp_dst_req;
reqrsp_rsp_t reqrsp_src_rsp, reqrsp_dst_rsp;

reqrsp_iso #(
.AddrWidth (AddrWidth),
.DataWidth (DataWidth),
.UserWidth (UserWidth),
.req_t (reqrsp_req_t),
.rsp_t (reqrsp_rsp_t),
.BypassReq (BypassReq),
Expand Down
11 changes: 9 additions & 2 deletions hw/reqrsp_interface/src/reqrsp_mux.sv
Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,8 @@ module reqrsp_mux #(
parameter int unsigned AddrWidth = 0,
/// Data width of the interface.
parameter int unsigned DataWidth = 0,
/// User width of the interface.
parameter int unsigned UserWidth = 0,
/// Request type.
parameter type req_t = logic,
/// Response type.
Expand All @@ -39,8 +41,9 @@ module reqrsp_mux #(
typedef logic [AddrWidth-1:0] addr_t;
typedef logic [DataWidth-1:0] data_t;
typedef logic [DataWidth/8-1:0] strb_t;
typedef logic [UserWidth-1:0] user_t;

`REQRSP_TYPEDEF_REQ_CHAN_T(req_chan_t, addr_t, data_t, strb_t)
`REQRSP_TYPEDEF_REQ_CHAN_T(req_chan_t, addr_t, data_t, strb_t, user_t)

localparam int unsigned LogNrPorts = cf_math_pkg::idx_width(NrPorts);

Expand Down Expand Up @@ -159,6 +162,8 @@ module reqrsp_mux_intf #(
parameter int unsigned AddrWidth = 0,
/// Data width of the interface.
parameter int unsigned DataWidth = 0,
/// User width of the interface.
parameter int unsigned UserWidth = 0,
/// Amount of outstanding responses. Determines the FIFO size.
parameter int unsigned RespDepth = 8,
/// Cut timing paths on the request path. Incurs a cycle additional latency.
Expand All @@ -175,8 +180,9 @@ module reqrsp_mux_intf #(
typedef logic [AddrWidth-1:0] addr_t;
typedef logic [DataWidth-1:0] data_t;
typedef logic [DataWidth/8-1:0] strb_t;
typedef logic [UserWidth-1:0] user_t;

`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)

reqrsp_req_t [NrPorts-1:0] reqrsp_slv_req;
reqrsp_rsp_t [NrPorts-1:0] reqrsp_slv_rsp;
Expand All @@ -188,6 +194,7 @@ module reqrsp_mux_intf #(
.NrPorts (NrPorts),
.AddrWidth (AddrWidth),
.DataWidth (DataWidth),
.UserWidth (UserWidth),
.req_t (reqrsp_req_t),
.rsp_t (reqrsp_rsp_t),
.RespDepth (RespDepth),
Expand Down
18 changes: 7 additions & 11 deletions hw/reqrsp_interface/src/reqrsp_to_axi.sv
Original file line number Diff line number Diff line change
Expand Up @@ -48,15 +48,13 @@ module reqrsp_to_axi import reqrsp_pkg::*; #(
parameter int unsigned ID = 0,
/// Data width of bus, must be 32 or 64.
parameter int unsigned DataWidth = 32'b0,
parameter int unsigned UserWidth = 32'b0,
parameter type reqrsp_req_t = logic,
parameter type reqrsp_rsp_t = logic,
parameter type axi_req_t = logic,
parameter type axi_rsp_t = logic
) (
input logic clk_i,
input logic rst_ni,
input logic [UserWidth-1:0] user_i,
input reqrsp_req_t reqrsp_req_i,
output reqrsp_rsp_t reqrsp_rsp_o,
output axi_req_t axi_req_o,
Expand Down Expand Up @@ -175,7 +173,7 @@ module reqrsp_to_axi import reqrsp_pkg::*; #(
assign axi_req_o.ar.lock = (reqrsp_req_i.q.amo == AMOLR);
assign axi_req_o.ar.cache = axi_pkg::CACHE_MODIFIABLE;
assign axi_req_o.ar.id = $unsigned(ID);
assign axi_req_o.ar.user = user_i;
assign axi_req_o.ar.user = reqrsp_req_i.q.user;
assign axi_req_o.ar_valid = q_valid_read;
assign q_ready_read = axi_rsp_i.ar_ready;

Expand All @@ -190,11 +188,11 @@ module reqrsp_to_axi import reqrsp_pkg::*; #(
assign axi_req_o.aw.lock = (reqrsp_req_i.q.amo == AMOSC);
assign axi_req_o.aw.cache = axi_pkg::CACHE_MODIFIABLE;
assign axi_req_o.aw.id = $unsigned(ID);
assign axi_req_o.aw.user = user_i;
assign axi_req_o.aw.user = reqrsp_req_i.q.user;
assign axi_req_o.w.data = write_data;
assign axi_req_o.w.strb = reqrsp_req_i.q.strb;
assign axi_req_o.w.last = 1'b1;
assign axi_req_o.w.user = user_i;
assign axi_req_o.w.user = reqrsp_req_i.q.user;

// Both channels need to handshake (independently).
stream_fork #(
Expand Down Expand Up @@ -305,12 +303,11 @@ module reqrsp_to_axi_intf #(
parameter int unsigned AddrWidth = 32'd0,
/// AXI and REQRSP data width.
parameter int unsigned DataWidth = 32'd0,
/// AXI user width.
parameter int unsigned AxiUserWidth = 32'd0
/// AXI and REQRSP user width.
parameter int unsigned UserWidth = 32'd0
) (
input logic clk_i,
input logic rst_ni,
input logic [AxiUserWidth-1:0] user_i,
REQRSP_BUS reqrsp,
AXI_BUS axi
);
Expand All @@ -319,9 +316,9 @@ module reqrsp_to_axi_intf #(
typedef logic [DataWidth-1:0] data_t;
typedef logic [DataWidth/8-1:0] strb_t;
typedef logic [AxiIdWidth-1:0] id_t;
typedef logic [AxiUserWidth-1:0] user_t;
typedef logic [UserWidth-1:0] user_t;

`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
`REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t)

`AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
`AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
Expand All @@ -347,7 +344,6 @@ module reqrsp_to_axi_intf #(
) i_reqrsp_to_axi (
.clk_i,
.rst_ni,
.user_i,
.reqrsp_req_i (reqrsp_req),
.reqrsp_rsp_o (reqrsp_rsp),
.axi_req_o (axi_req),
Expand Down
3 changes: 1 addition & 2 deletions hw/reqrsp_interface/test/reqrsp_to_axi_tb.sv
Original file line number Diff line number Diff line change
Expand Up @@ -58,11 +58,10 @@ module reqrsp_to_axi_tb import reqrsp_pkg::*; #(
.AxiIdWidth (IW),
.AddrWidth (AW),
.DataWidth (DW),
.AxiUserWidth (UW)
.UserWidth (UW)
) i_reqrsp_to_axi (
.clk_i (clk),
.rst_ni (rst_n),
.user_i ('0),
.reqrsp (master),
.axi (slave)
);
Expand Down
5 changes: 3 additions & 2 deletions hw/snitch/src/riscv_instr.sv
Original file line number Diff line number Diff line change
Expand Up @@ -327,7 +327,7 @@ package riscv_instr;
localparam logic [31:0] DMSTAT = 32'b0000101?????00000000?????0101011;
localparam logic [31:0] DMSTR = 32'b0000110??????????000000000101011;
localparam logic [31:0] DMREP = 32'b000011100000?????000000000101011;
localparam logic [31:0] DMMCAST = 32'b000100000000?????000000000101011;
localparam logic [31:0] DMUSER = 32'b0001000??????????000000000101011;
localparam logic [31:0] FREP_O = 32'b????????????????????????10001011;
localparam logic [31:0] IREP = 32'b?????????????????????????0111111;
localparam logic [31:0] SCFGRI = 32'b????????????00000001?????0101011;
Expand Down Expand Up @@ -1140,7 +1140,8 @@ package riscv_instr;
localparam logic [11:0] CSR_FPMODE = 12'h7c1;
localparam logic [11:0] CSR_BARRIER = 12'h7c2;
localparam logic [11:0] CSR_SC = 12'h7c3;
localparam logic [11:0] CSR_MCAST = 12'h7c4;
localparam logic [11:0] CSR_USER_LOW = 12'h7c4;
localparam logic [11:0] CSR_USER_HIGH = 12'h7c5;
localparam logic [11:0] CSR_HTIMEDELTAH = 12'h615;
localparam logic [11:0] CSR_CYCLEH = 12'hc80;
localparam logic [11:0] CSR_TIMEH = 12'hc81;
Expand Down
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