feat: add zvfofp8min extension

.github/actions/singularity-setup/action.yml

@@ -19,10 +19,12 @@ runs:
             .home/.gems
             node_modules
           key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }}
+          fail-on-cache-miss: false
       - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }}
         name: Build container
         run: ./bin/build_container
         shell: bash
+
       - name: Setup project
         run: ./bin/setup
         shell: bash

cfgs/example_rv64_with_overlay.yaml

@@ -418,6 +418,19 @@ params:
   # corresponds to the `GEILEN` parameter in the RVI specs
   NUM_EXTERNAL_GUEST_INTERRUPTS: 4
 
+  # AIA (Advanced Interrupt Architecture) configuration parameters
+  # Required for Smaia/Ssaia extensions
+
+  # Machine Virtual Interrupts configuration
+  # Specifies which interrupt numbers (13-63) are supported as writable bits in mvien/mvip
+  MACHINE_VIRTUAL_INTERRUPTS:
+    [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
+
+  # Machine Virtual Interrupts that are always enabled (read-only-1)
+  # Must be a subset of MACHINE_VIRTUAL_INTERRUPTS
+  # Empty array means no interrupts are forced to always-enabled
+  MACHINE_VIRTUAL_INTERRUPTS_ALWAYS_ENABLED: []
+
   # Endianness of data in M-mode. Can be one of:
   #
   #  * little:  M-mode data is always little endian

spec/custom/isa/qc_iu/inst/Xqci/qc.mop.yaml

@@ -0,0 +1,43 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: qc.mop
+long_name: Multiplication with odd parameter
+description: |
+  Example instruction demonstrating the transform field functionality for ensuring
+  a field value is always odd by applying the transformation (var << 1) | 1
+definedBy:
+  anyOf:
+    - name: Xqci
+      version: ">= 0.2"
+    - Xqciac
+base: 32
+encoding:
+  match: 01---------------111-----0001011
+  variables:
+    - name: n
+      location: 29-25
+      transform: "(var << 1) | 1"
+      not: 0
+    - name: rs2
+      location: 24-20
+      not: 0
+    - name: rs1
+      location: 19-15
+      not: 0
+    - name: rd
+      location: 11-7
+      not: 0
+assembly: " xd, xs1, xs2, n"
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  // n is guaranteed to be odd due to the transform (var << 1) | 1
+  X[rd] = X[rs1] * X[rs2] * n;