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1. vtr-verilog-to-routing vtr-verilog-to-routing Public

   Forked from verilog-to-routing/vtr-verilog-to-routing

   Verilog to Routing -- Open Source CAD Flow for FPGA Research

   C++

2. rad_gen rad_gen Public

   Forked from StephenMoreOSU/rad_gen

   RAD-Gen is a tool for silicon area/timing/power implementation results of hard (ASIC) components, FPGA fabric circuitry, and circuit modeling of 3D devices/packaging

   Verilog