Merge pull request #70 from korken89/generic-timer-irq-example

Working timer example with IRQs

Author: jonathanpallant

examples/mps3-an536/Cargo.toml

@@ -41,3 +41,7 @@ required-features = ["gic"]
 [[bin]]
 name = "gic-unified-irq"
 required-features = ["gic"]
+
+[[bin]]
+name = "generic_timer_irq"
+required-features = ["gic"]

examples/mps3-an536/reference/generic_timer_irq-armv8r-none-eabihf.out

@@ -0,0 +1,48 @@
+Found PERIPHBASE 0xf0000000
+Creating GIC driver @ 0xf0000000 / 0xf0100000
+Calling git.setup(0)
+Configure Timer Interrupt...
+Enabling interrupts...
+CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=1 F=1 T=0 MODE=Ok(Sys) }
+CPSR: CPSR { N=0 Z=1 C=1 V=0 Q=0 J=0 E=0 A=0 I=0 F=1 T=0 MODE=Ok(Sys) }
+  > IRQ
+    - Timer fired, resetting
+  < IRQ
+Main loop wake up 0
+  > IRQ
+    - Timer fired, resetting
+  < IRQ
+Main loop wake up 1
+  > IRQ
+    - Timer fired, resetting
+  < IRQ
+Main loop wake up 2
+  > IRQ
+    - Timer fired, resetting
+  < IRQ
+Main loop wake up 3
+  > IRQ
+    - Timer fired, resetting
+  < IRQ
+Main loop wake up 4
+  > IRQ
+    - Timer fired, resetting
+  < IRQ
+Main loop wake up 5
+  > IRQ
+    - Timer fired, resetting
+  < IRQ
+Main loop wake up 6
+  > IRQ
+    - Timer fired, resetting
+  < IRQ
+Main loop wake up 7
+  > IRQ
+    - Timer fired, resetting
+  < IRQ
+Main loop wake up 8
+  > IRQ
+    - Timer fired, resetting
+  < IRQ
+Main loop wake up 9
+Timer IRQ test completed OK

examples/mps3-an536/src/bin/generic_timer_irq.rs

@@ -0,0 +1,118 @@
+//! Generic-timer example for Arm Cortex-R52, with interrupts firing.
+
+#![no_std]
+#![no_main]
+
+use arm_gic::{
+    gicv3::{GicCpuInterface, GicV3, Group, InterruptGroup},
+    IntId, UniqueMmioPointer,
+};
+use core::ptr::NonNull;
+use cortex_ar::generic_timer::{El1VirtualTimer, GenericTimer};
+use cortex_r_rt::{entry, irq};
+use mps3_an536 as _;
+use semihosting::println;
+
+/// Offset from PERIPHBASE for GIC Distributor
+const GICD_BASE_OFFSET: usize = 0x0000_0000usize;
+
+/// Offset from PERIPHBASE for the first GIC Redistributor
+const GICR_BASE_OFFSET: usize = 0x0010_0000usize;
+
+/// The PPI for the virutal timer, according to the Cortex-R52 Technical Reference Manual,
+/// Table 10-3: PPI assignments.
+///
+/// This corresponds to Interrupt ID 27.
+const VIRTUAL_TIMER_PPI: IntId = IntId::ppi(11);
+
+/// The entry-point to the Rust application.
+///
+/// It is called by the start-up code in `cortex-r-rt`.
+#[entry]
+fn main() -> ! {
+    // Get the GIC address by reading CBAR
+    let periphbase = cortex_ar::register::ImpCbar::read().periphbase();
+    println!("Found PERIPHBASE {:010p}", periphbase);
+    let gicd_base = periphbase.wrapping_byte_add(GICD_BASE_OFFSET);
+    let gicr_base = periphbase.wrapping_byte_add(GICR_BASE_OFFSET);
+
+    // Initialise the GIC.
+    println!(
+        "Creating GIC driver @ {:010p} / {:010p}",
+        gicd_base, gicr_base
+    );
+    let gicd = unsafe { UniqueMmioPointer::new(NonNull::new(gicd_base.cast()).unwrap()) };
+    let gicr = NonNull::new(gicr_base.cast()).unwrap();
+    let mut gic = unsafe { GicV3::new(gicd, gicr, 1, false) };
+
+    println!("Calling git.setup(0)");
+    gic.setup(0);
+    GicCpuInterface::set_priority_mask(0x80);
+
+    println!("Configure Timer Interrupt...");
+    gic.set_interrupt_priority(VIRTUAL_TIMER_PPI, Some(0), 0x31)
+        .unwrap();
+    gic.set_group(VIRTUAL_TIMER_PPI, Some(0), Group::Group1NS)
+        .unwrap();
+    gic.enable_interrupt(VIRTUAL_TIMER_PPI, Some(0), true)
+        .unwrap();
+
+    // Create virtual timer, run as up-counter.
+    let mut vgt = unsafe { El1VirtualTimer::new() };
+    vgt.enable(true);
+    vgt.interrupt_mask(false);
+    vgt.counter_compare_set(vgt.counter().wrapping_add(vgt.frequency_hz() as u64));
+
+    drop(vgt); // Drop to free the timer handle.
+
+    println!("Enabling interrupts...");
+    dump_cpsr();
+    unsafe {
+        cortex_ar::interrupt::enable();
+    }
+    dump_cpsr();
+
+    let mut count: u32 = 0;
+    loop {
+        cortex_ar::asm::wfi();
+        println!("Main loop wake up {}", count);
+        count = count.wrapping_add(1);
+
+        if count == 10 {
+            println!("Timer IRQ test completed OK");
+            semihosting::process::exit(0);
+        }
+    }
+}
+
+fn dump_cpsr() {
+    let cpsr = cortex_ar::register::Cpsr::read();
+    println!("CPSR: {:?}", cpsr);
+}
+
+#[irq]
+fn irq_handler() {
+    println!("  > IRQ");
+    while let Some(int_id) = GicCpuInterface::get_and_acknowledge_interrupt(InterruptGroup::Group1)
+    {
+        match int_id {
+            VIRTUAL_TIMER_PPI => handle_timer_irq(),
+            _ => unreachable!("We handle all enabled IRQs"),
+        }
+        GicCpuInterface::end_interrupt(int_id, InterruptGroup::Group1);
+    }
+    println!("  < IRQ");
+}
+
+/// Run when the timer IRQ fires
+fn handle_timer_irq() {
+    // SAFETY: We drop en other time handle in main, this is the only active handle.
+    let mut vgt = unsafe { El1VirtualTimer::new() };
+    // trigger a timer in 0.2 seconds
+    vgt.counter_compare_set(
+        vgt.counter_compare()
+            .wrapping_add(vgt.frequency_hz() as u64 / 5),
+    );
+
+    println!("    - Timer fired, resetting");
+}