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Add cache maintenance regs and simple API for inner cache maintenance #40
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@jonathanpallant I wrote the API with systems in mind where the cache geometry/paramters are fixed.. But maybe it would be a good idea to be able to read these geometry parameters from the corresponding CP15 registers as well? then, an alternative API for the high level clean/invalidate API which expects these geometry parameters would probably be a good idea as well.. |
I'm OK with starting out only supporting people who know precisely which chip they are running on. |
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Similarly to #39, this was used and tested this as part of a zynq7000 ethernet implementation. |
It would be nice to have automated testing, but that is quite tricky.. The "easiest" way would be to use some QEMU device which uses DMA only interfacing with main memory, where cache maintenance is absolutely necessary for it to work. The https://www.qemu.org/docs/master/system/arm/xlnx-zynq.html appears to support the PrimeCell DMA, but that is a DMA where I would have to write some sort of mini compiler for their DSL.. and while the zynq seems to support ethernet, this would be a lot more complicated than a memory-to-memory DMA because now the ethernet interface needs to be mocked/checked now. NOTE: Does QEMU even emulate the L1/L2 caches? If it does not, then this can only be tested with real hardware |
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QEMU does JIT translation to native code, so I suspect it does not emulate cache lines. The Arm Fixed Virtual Platform seems to simulate caches (see https://developer.arm.com/documentation/100966/1128/BaseR-Platform-FVPs/FVP-BaseR-Cortex-R52). Not free though. |
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Whilst we may not have a simulator that perfectly emulates the cache behaviour, some example programs would be useful here.
Opened #47, but this is fine for now |
Something went wrong with the merge bot |
still needs to be tested, and I might add the API which cleans/invalidates by virtual address as well because it is required for range based cleaning/invalidation