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stdarch-test: various cleanups #1860

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7ee416d
update `Cargo.lock`
folkertdev Jul 10, 2025
939a51c
`stdarch-test`: use `std::sync::LazyLock` instead of `lazy_static!`
folkertdev Jul 10, 2025
48facc3
`stdarch-test`: misc cleanups
folkertdev Jul 10, 2025
70d77c9
`stdarch-test`: error if only part of an instruction matched
folkertdev Jul 10, 2025
f0a3920
s390x: fix tests that matched on prefix of instruction
folkertdev Jul 10, 2025
e30131f
aarch64/arm: fix tests that matched on prefix of instruction
folkertdev Jul 10, 2025
06b6db7
`aarch64`: check for `zip1` and `zip2`
folkertdev Jul 15, 2025
bac75c9
`aarch64`: check for `uzp1` and `uzp2`
folkertdev Jul 15, 2025
b9a9fea
`aarch64`: check for `trn1` and `trn2`
folkertdev Jul 15, 2025
ad920f5
test for the high version of a number of instructions
folkertdev Jul 17, 2025
91c95eb
`stdarch-test`: for now, allow if only part of an instruction matched
folkertdev Jul 10, 2025
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13 changes: 6 additions & 7 deletions Cargo.lock
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58 changes: 29 additions & 29 deletions crates/core_arch/src/aarch64/neon/generated.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,7 @@ pub fn __crc32d(crc: u32, data: u64) -> u32 {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal))]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))]
pub fn vabal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
unsafe {
let d: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
Expand All @@ -66,7 +66,7 @@ pub fn vabal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal))]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))]
pub fn vabal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
unsafe {
let d: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
Expand All @@ -81,7 +81,7 @@ pub fn vabal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal))]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))]
pub fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
unsafe {
let d: int32x2_t = simd_shuffle!(b, b, [2, 3]);
Expand All @@ -96,7 +96,7 @@ pub fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal))]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))]
pub fn vabal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t {
unsafe {
let d: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
Expand All @@ -110,7 +110,7 @@ pub fn vabal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal))]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))]
pub fn vabal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t {
unsafe {
let d: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
Expand All @@ -124,7 +124,7 @@ pub fn vabal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal))]
#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))]
pub fn vabal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t {
unsafe {
let d: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
Expand Down Expand Up @@ -197,7 +197,7 @@ pub fn vabdh_f16(a: f16, b: f16) -> f16 {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(sabdl))]
#[cfg_attr(test, assert_instr(sabdl2))]
pub fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
unsafe {
let c: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
Expand All @@ -211,7 +211,7 @@ pub fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(sabdl))]
#[cfg_attr(test, assert_instr(sabdl2))]
pub fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
unsafe {
let c: int32x2_t = simd_shuffle!(a, a, [2, 3]);
Expand All @@ -225,7 +225,7 @@ pub fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(sabdl))]
#[cfg_attr(test, assert_instr(sabdl2))]
pub fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
unsafe {
let c: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
Expand All @@ -238,7 +238,7 @@ pub fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(uabdl))]
#[cfg_attr(test, assert_instr(uabdl2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
unsafe {
Expand All @@ -251,7 +251,7 @@ pub fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(uabdl))]
#[cfg_attr(test, assert_instr(uabdl2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vabdl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
unsafe {
Expand All @@ -264,7 +264,7 @@ pub fn vabdl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(uabdl))]
#[cfg_attr(test, assert_instr(uabdl2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vabdl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
unsafe {
Expand Down Expand Up @@ -7177,7 +7177,7 @@ pub fn vcvt_high_f32_f16(a: float16x8_t) -> float32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtn))]
#[cfg_attr(test, assert_instr(fcvtn2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
unsafe { simd_shuffle!(a, simd_cast(b), [0, 1, 2, 3]) }
Expand All @@ -7186,7 +7186,7 @@ pub fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f64_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtl))]
#[cfg_attr(test, assert_instr(fcvtl2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvt_high_f64_f32(a: float32x4_t) -> float64x2_t {
unsafe {
Expand Down Expand Up @@ -9286,7 +9286,7 @@ pub fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t {
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_high_f32_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtxn))]
#[cfg_attr(test, assert_instr(fcvtxn2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvtx_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
unsafe { simd_shuffle!(a, vcvtx_f32_f64(b), [0, 1, 2, 3]) }
Expand Down Expand Up @@ -14893,7 +14893,7 @@ pub fn vmull_high_n_u32(a: uint32x4_t, b: u32) -> uint64x2_t {
#[inline]
#[target_feature(enable = "neon,aes")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(pmull))]
#[cfg_attr(test, assert_instr(pmull2))]
pub fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 {
unsafe { vmull_p64(simd_extract!(a, 1), simd_extract!(b, 1)) }
}
Expand All @@ -14902,7 +14902,7 @@ pub fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(pmull))]
#[cfg_attr(test, assert_instr(pmull2))]
pub fn vmull_high_p8(a: poly8x16_t, b: poly8x16_t) -> poly16x8_t {
unsafe {
let a: poly8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
Expand Down Expand Up @@ -26497,7 +26497,7 @@ pub fn vsubh_f16(a: f16, b: f16) -> f16 {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(ssubl))]
#[cfg_attr(test, assert_instr(ssubl2))]
pub fn vsubl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
unsafe {
let c: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
Expand All @@ -26512,7 +26512,7 @@ pub fn vsubl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(ssubl))]
#[cfg_attr(test, assert_instr(ssubl2))]
pub fn vsubl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
unsafe {
let c: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
Expand All @@ -26527,7 +26527,7 @@ pub fn vsubl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(ssubl))]
#[cfg_attr(test, assert_instr(ssubl2))]
pub fn vsubl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
unsafe {
let c: int32x2_t = simd_shuffle!(a, a, [2, 3]);
Expand All @@ -26542,7 +26542,7 @@ pub fn vsubl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(usubl))]
#[cfg_attr(test, assert_instr(usubl2))]
pub fn vsubl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
unsafe {
let c: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
Expand All @@ -26557,7 +26557,7 @@ pub fn vsubl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(usubl))]
#[cfg_attr(test, assert_instr(usubl2))]
pub fn vsubl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
unsafe {
let c: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
Expand All @@ -26572,7 +26572,7 @@ pub fn vsubl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(usubl))]
#[cfg_attr(test, assert_instr(usubl2))]
pub fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
unsafe {
let c: uint32x2_t = simd_shuffle!(a, a, [2, 3]);
Expand All @@ -26587,7 +26587,7 @@ pub fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(ssubw))]
#[cfg_attr(test, assert_instr(ssubw2))]
pub fn vsubw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
unsafe {
let c: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
Expand All @@ -26599,7 +26599,7 @@ pub fn vsubw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(ssubw))]
#[cfg_attr(test, assert_instr(ssubw2))]
pub fn vsubw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
unsafe {
let c: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
Expand All @@ -26611,7 +26611,7 @@ pub fn vsubw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(ssubw))]
#[cfg_attr(test, assert_instr(ssubw2))]
pub fn vsubw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
unsafe {
let c: int32x2_t = simd_shuffle!(b, b, [2, 3]);
Expand All @@ -26623,7 +26623,7 @@ pub fn vsubw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(usubw))]
#[cfg_attr(test, assert_instr(usubw2))]
pub fn vsubw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
unsafe {
let c: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
Expand All @@ -26635,7 +26635,7 @@ pub fn vsubw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(usubw))]
#[cfg_attr(test, assert_instr(usubw2))]
pub fn vsubw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
unsafe {
let c: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
Expand All @@ -26647,7 +26647,7 @@ pub fn vsubw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
#[inline]
#[target_feature(enable = "neon")]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
#[cfg_attr(test, assert_instr(usubw))]
#[cfg_attr(test, assert_instr(usubw2))]
pub fn vsubw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
unsafe {
let c: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
Expand Down
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