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feat: update rust edition to 2024 and change asm! to naked_asm! #61

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Feb 9, 2025
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feat: update rust edition to 2024 and change asm! to naked_asm! #61

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576 changes: 528 additions & 48 deletions Cargo.lock
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4 changes: 2 additions & 2 deletions Cargo.toml
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Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
[workspace]
resolver = "2"
resolver = "3"
members = ["prototyper", "bench-kernel", "test-kernel", "supervisor", "xtask"]

[workspace.package]
edition = "2021"
edition = "2024"
license = "MulanPSL-2.0 OR MIT"
repository = "https://github.com/rustsbi/prototyper"

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127 changes: 67 additions & 60 deletions bench-kernel/src/main.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -8,16 +8,19 @@ extern crate rcore_console;

use core::mem::MaybeUninit;
use core::sync::{atomic::AtomicBool, atomic::AtomicU64, atomic::Ordering};
use core::{arch::asm, ptr::null};
use core::{
arch::{asm, naked_asm},
ptr::null,
};
use log::*;
use sbi::SbiRet;
use sbi_spec::binary::{HartMask, MaskError};
use sbi_spec::hsm::hart_state;
use sbi_testing::sbi;
use serde::Deserialize;
use serde_device_tree::{
buildin::{Node, NodeSeq, Reg, StrSeq},
Dtb, DtbPtr,
buildin::{Node, NodeSeq, Reg, StrSeq},
};
use uart16550::Uart16550;

Expand All @@ -28,29 +31,30 @@ const RISCV_IMAGE_MAGIC2: u32 = 0x05435352; /* Magic number 2, little endian, "R

/// boot header
#[naked]
#[no_mangle]
#[link_section = ".head.text"]
#[unsafe(no_mangle)]
#[unsafe(link_section = ".head.text")]
unsafe extern "C" fn _boot_header() -> ! {
asm!(
"j _start",
".word 0",
".balign 8",
".dword 0x200000",
".dword iend - istart",
".dword {RISCV_HEAD_FLAGS}",
".word {RISCV_HEADER_VERSION}",
".word 0",
".dword 0",
".dword {RISCV_IMAGE_MAGIC}",
".balign 4",
".word {RISCV_IMAGE_MAGIC2}",
".word 0",
RISCV_HEAD_FLAGS = const RISCV_HEAD_FLAGS,
RISCV_HEADER_VERSION = const RISCV_HEADER_VERSION,
RISCV_IMAGE_MAGIC = const RISCV_IMAGE_MAGIC,
RISCV_IMAGE_MAGIC2 = const RISCV_IMAGE_MAGIC2,
options(noreturn)
);
unsafe {
naked_asm!(
"j _start",
".word 0",
".balign 8",
".dword 0x200000",
".dword iend - istart",
".dword {RISCV_HEAD_FLAGS}",
".word {RISCV_HEADER_VERSION}",
".word 0",
".dword 0",
".dword {RISCV_IMAGE_MAGIC}",
".balign 4",
".word {RISCV_IMAGE_MAGIC2}",
".word 0",
RISCV_HEAD_FLAGS = const RISCV_HEAD_FLAGS,
RISCV_HEADER_VERSION = const RISCV_HEADER_VERSION,
RISCV_IMAGE_MAGIC = const RISCV_IMAGE_MAGIC,
RISCV_IMAGE_MAGIC2 = const RISCV_IMAGE_MAGIC2,
);
}
}

const STACK_SIZE: usize = 512 * 1024; // 512 KiB
Expand All @@ -67,16 +71,16 @@ impl HartStack {
}
}

#[link_section = ".bss.uninit"]
#[unsafe(link_section = ".bss.uninit")]
static mut STACK: HartStack = HartStack::new();
#[link_section = ".bss.uninit"]
#[unsafe(link_section = ".bss.uninit")]
static mut HART_STACK: [HartStack; MAX_HART_NUM] = [HartStack::new(); MAX_HART_NUM];
#[link_section = ".bss.uninit"]
#[unsafe(link_section = ".bss.uninit")]
static mut IPI_SENT: [MaybeUninit<AtomicBool>; MAX_HART_NUM] =
[const { MaybeUninit::uninit() }; MAX_HART_NUM];
#[link_section = ".bss.uninit"]
#[unsafe(link_section = ".bss.uninit")]
static mut SMP_COUNT: usize = 0;
#[link_section = ".bss.uninit"]
#[unsafe(link_section = ".bss.uninit")]
static mut BOOT_HART_ID: usize = 0;

/// 内核入口。
Expand All @@ -85,49 +89,52 @@ static mut BOOT_HART_ID: usize = 0;
///
/// 裸函数。
#[naked]
#[no_mangle]
#[link_section = ".text.entry"]
#[unsafe(no_mangle)]
#[unsafe(link_section = ".text.entry")]
unsafe extern "C" fn _start(hartid: usize, device_tree_paddr: usize) -> ! {
asm!(
// clear bss segment
" la t0, sbss
unsafe {
naked_asm!(
// clear bss segment
" la t0, sbss
la t1, ebss
1: bgeu t0, t1, 2f
sd zero, 0(t0)
addi t0, t0, 8
j 1b",
"2:",
" la sp, {stack} + {stack_size}",
" j {main}",
stack_size = const STACK_SIZE,
stack = sym STACK,
main = sym rust_main,
options(noreturn),
)
"2:",
" la sp, {stack} + {stack_size}",
" j {main}",
stack_size = const STACK_SIZE,
stack = sym STACK,
main = sym rust_main,
)
}
}

#[naked]
#[no_mangle]
unsafe extern "C" fn init_hart(hartid: usize, opaque: usize) {
asm!(
"add sp, a1, zero",
"csrw sscratch, sp",
"call {init_main}",
init_main = sym init_main,
options(noreturn),
)
#[unsafe(no_mangle)]
extern "C" fn init_hart(hartid: usize, opaque: usize) {
unsafe {
naked_asm!(
"add sp, a1, zero",
"csrw sscratch, sp",
"call {init_main}",
init_main = sym init_main,
)
}
}

#[naked]
#[no_mangle]
unsafe extern "C" fn core_send_ipi(hartid: usize, opaque: usize) {
asm!(
"add sp, a1, zero",
"csrw sscratch, sp",
"call {send_ipi}",
send_ipi = sym send_ipi,
options(noreturn),
)
#[unsafe(no_mangle)]
extern "C" fn core_send_ipi(hartid: usize, opaque: usize) {
unsafe {
naked_asm!(
"add sp, a1, zero",
"csrw sscratch, sp",
"call {send_ipi}",
send_ipi = sym send_ipi,
)
}
}

extern "C" fn send_ipi(hartid: usize) -> ! {
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12 changes: 6 additions & 6 deletions prototyper/Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -9,20 +9,20 @@ repository.workspace = true
forced-target = "riscv64imac-unknown-none-elf"

[dependencies]
aclint = "0.0.0"
log = "0.4.21"
aclint = "=0.1.0"
log = "0.4"
panic-halt = "1.0.0"
riscv = "0.11.1"
rustsbi = { version = "0.4.0", features = ["machine"] }
sbi-spec = { version = "0.0.8", features = ["legacy"] }
serde = { version = "1.0.202", default-features = false, features = ["derive"] }
sifive-test-device = "0.0.0"
spin = "0.9.8"
uart16550 = "0.0.1"
riscv-decode = "0.2.1"
cfg-if = "1.0.0"
buddy_system_allocator = "0.11.0"
fast-trap = { version = "0.0.1", features = ["riscv-m"] }
rustsbi = { version = "0.4.0", features = ["machine"] }
sbi-spec = { version = "0.0.8", features = ["legacy"] }
serde = { version = "1.0.202", default-features = false, features = ["derive"] }
fast-trap = { version = "0.1.0", features = ["riscv-m"] }
serde-device-tree = { git = "https://github.com/rustsbi/serde-device-tree", default-features = false }
uart_xilinx = { git = "https://github.com/duskmoon314/uart-rs/" }
xuantie-riscv = { git= "https://github.com/rustsbi/xuantie" }
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2 changes: 1 addition & 1 deletion prototyper/src/devicetree.rs
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
use serde::Deserialize;
use serde_device_tree::{
buildin::{Node, NodeSeq, Reg, StrSeq},
Dtb, DtbPtr,
buildin::{Node, NodeSeq, Reg, StrSeq},
};

use core::ops::Range;
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