RVF Workshop 2025
This page contains information about our contribution to the "3rd European RISC-V and Firmware Workshop (RVF)" taking place in Vienna between 18.-19.09.2025.
Title: Trace-based Performance Profiling of RISC-V Applications
Topic: Virtual Prototyping, Profiling, Static/Dynamic Analysis
Contributors:
- Philipp van Kempen, Technical University of Munich, DE
- Eyck-Alexander Jentzsch, MINRES Technologies GmbH, DE
Abstract: This presentation introduces a Python-based framework for trace-based performance profiling of RISC-V applications. Unlike traditional sample-based profilers, trace-based approaches provide fine-grained insights into program behavior, enabling precise identification of performance bottlenecks. We address the challenges of unifying diverse ISS trace formats, leveraging debug information to reconstruct call stacks, and accurately aggregating execution costs. The talk will also cover trace compression, scalability, and ongoing work, and will conclude with a short live demo utilizing multiple profiling backends.
Projects: Scale4Edge project (German, BMBF (National))
Work in Progress
Current implementation is available on the tgc-support branch.
Detailed documentation on how to use the refactored flow and reproduce the presented results will be posted soon after cleaning up the codebase :)
This work has been developed in the ZuSE project Scale4Edge. Scale4Edge is funded by the German Federal Ministry of Research, Technology and Space (BMFTR) (reference numbers: 16ME0122K-16ME0140+16ME0465+16ME0900+16ME0901). The authors are responsible for the content of this publication.
