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UC Berkeley Architecture Research

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  1. chipyard chipyard Public

    An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

    Scala 2k 750

  2. chiseltest chiseltest Public archive

    The batteries-included testing and formal verification library for Chisel-based RTL designs.

    Scala 233 76

  3. dsptools dsptools Public

    A Library of Chisel3 Tools for Digital Signal Processing

    Scala 238 40

  4. chisel-tutorial chisel-tutorial Public

    chisel tutorial exercises and answers

    Scala 736 201

Repositories

Showing 10 of 201 repositories
  • radiance Public
    ucb-bar/radiance’s past year of commit activity
    Scala 7 1 0 0 Updated Sep 3, 2025
  • autocomp Public
    ucb-bar/autocomp’s past year of commit activity
    Python 9 BSD-3-Clause 0 0 0 Updated Sep 3, 2025
  • xrsight Public

    A hardware–software co-design framework for developing and characterizing extended reality (XR) workloads on embedded systems-on-chip (SoCs).

    ucb-bar/xrsight’s past year of commit activity
    0 0 0 0 Updated Sep 2, 2025
  • tacit_decoder Public
    ucb-bar/tacit_decoder’s past year of commit activity
    Rust 5 1 0 1 Updated Sep 3, 2025
  • tacit Public

    Timing Accurate Core Instruction Trace

    ucb-bar/tacit’s past year of commit activity
    Scala 0 0 0 0 Updated Sep 2, 2025
  • chipyard Public

    An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

    ucb-bar/chipyard’s past year of commit activity
    Scala 1,950 BSD-3-Clause 750 151 (3 issues need help) 27 Updated Sep 2, 2025
  • cva6-wrapper Public

    Wrapper for ETH Ariane Core

    ucb-bar/cva6-wrapper’s past year of commit activity
    Scala 21 18 1 0 Updated Sep 2, 2025
  • nvdla-wrapper Public

    Wraps the NVDLA project for Chipyard integration

    ucb-bar/nvdla-wrapper’s past year of commit activity
    Verilog 21 10 5 0 Updated Sep 2, 2025
  • SteamVR-Bridge Public

    Codebase used for Berkeley Humanoid Lite teleoperation demonstration.

    ucb-bar/SteamVR-Bridge’s past year of commit activity
    Python 1 1 0 0 Updated Sep 2, 2025
  • vexiiriscv-tile Public

    Chisel wrapper for the SpinalHDL VexiiRiscv CPU implementation, implementing Chipyard compatibility

    ucb-bar/vexiiriscv-tile’s past year of commit activity
    Scala 2 BSD-3-Clause 0 0 0 Updated Sep 1, 2025
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