verilog-to-routing · soheilshahrouz · Sep 5, 2025 · Sep 5, 2025 · Sep 5, 2025 · Sep 5, 2025
diff --git a/libs/libarchfpga/src/echo_arch.cpp b/libs/libarchfpga/src/echo_arch.cpp
@@ -185,13 +185,13 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
     }
 
     switch (arch->sb_type) {
-        case (WILTON):
+        case e_switch_block_type::WILTON:
             fprintf(Echo, "\tSwitch Block: type wilton fs %d\n", arch->Fs);
             break;
-        case (UNIVERSAL):
+        case (e_switch_block_type::UNIVERSAL):
             fprintf(Echo, "\tSwitch Block: type universal fs %d\n", arch->Fs);
             break;
-        case (SUBSET):
+        case e_switch_block_type::SUBSET:
             fprintf(Echo, "\tSwitch Block: type subset fs %d\n", arch->Fs);
             break;
         default:
@@ -201,7 +201,7 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
     fprintf(Echo, "\tInput Connect Block Switch Name Within a Same Die: %s\n", arch->ipin_cblock_switch_name[ipin_cblock_switch_index_within_die].c_str());
 
     //if there is more than one layer available, print the connection block switch name that is used for connection between two dice
-    for (const auto& layout : arch->grid_layouts) {
+    for (const t_grid_def& layout : arch->grid_layouts) {
         int num_layers = (int)layout.layers.size();
         if (num_layers > 1) {
             fprintf(Echo, "\tInput Connect Block Switch Name Between Two Dice: %s\n", arch->ipin_cblock_switch_name[ipin_cblock_switch_index_between_dice].c_str());
@@ -257,14 +257,6 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
             //wire_switch == arch_opin_switch
             fprintf(Echo, "\t\t\t\ttype unidir mux_name for within die connections: %s\n",
                     arch->switches[seg.arch_wire_switch].name.c_str());
-            //if there is more than one layer available, print the segment switch name that is used for connection between two dice
-            for (const auto& layout : arch->grid_layouts) {
-                int num_layers = (int)layout.layers.size();
-                if (num_layers > 1) {
-                    fprintf(Echo, "\t\t\t\ttype unidir mux_name for between two dice connections: %s\n",
-                            arch->switches[seg.arch_inter_die_switch].name.c_str());
-                }
-            }
         } else { //Should be bidir
             fprintf(Echo, "\t\t\t\ttype bidir wire_switch %s arch_opin_switch %s\n",
                     arch->switches[seg.arch_wire_switch].name.c_str(),

diff --git a/libs/libarchfpga/src/logic_types.h b/libs/libarchfpga/src/logic_types.h
@@ -31,7 +31,9 @@ enum class e_parallel_axis {
     /** Y_AXIS: Data that describes an y-directed wire segment (CHANY) */
     Y_AXIS,
     /** BOTH_AXIS: Data that can be applied to both x-directed and y-directed wire segment */
-    BOTH_AXIS
+    BOTH_AXIS,
+    /** Z_AXIS: Data that describes an z-directed wire segment (CHANZ) */
+    Z_AXIS
 };
 
 /*

diff --git a/libs/libarchfpga/src/parse_switchblocks.cpp b/libs/libarchfpga/src/parse_switchblocks.cpp
@@ -35,7 +35,7 @@ using vtr::t_formula_data;
 /*---- Functions for Parsing Switchblocks from Architecture ----*/
 
 //Process the desired order of a wireconn
-static void parse_switchpoint_order(const char* order, SwitchPointOrder& switchpoint_order);
+static void parse_switchpoint_order(std::string_view order, e_switch_point_order& switchpoint_order);
 
 /**
  * @brief Parses an inline `<wireconn>` node using its attributes.
@@ -86,7 +86,7 @@ static void parse_comma_separated_wire_points(const char* ch, std::vector<t_wire
 static void parse_num_conns(std::string num_conns, t_wireconn_inf& wireconn);
 
 /* Set connection from_side and to_side for custom switch block pattern*/
-static void set_switch_func_type(SBSideConnection& conn, const char* func_type);
+static void set_switch_func_type(SBSideConnection& conn, std::string_view func_type);
 
 /* parse switch_override in wireconn */
 static void parse_switch_override(const char* switch_override, t_wireconn_inf& wireconn, const std::vector<t_arch_switch_inf>& switches);
@@ -282,13 +282,13 @@ static t_wire_switchpoints parse_wireconn_from_to_node(pugi::xml_node node, cons
     return wire_switchpoints;
 }
 
-static void parse_switchpoint_order(const char* order, SwitchPointOrder& switchpoint_order) {
-    if (order == std::string("")) {
-        switchpoint_order = SwitchPointOrder::SHUFFLED; //Default
-    } else if (order == std::string("fixed")) {
-        switchpoint_order = SwitchPointOrder::FIXED;
-    } else if (order == std::string("shuffled")) {
-        switchpoint_order = SwitchPointOrder::SHUFFLED;
+static void parse_switchpoint_order(std::string_view order, e_switch_point_order& switchpoint_order) {
+    if (order == "") {
+        switchpoint_order = e_switch_point_order::SHUFFLED; //Default
+    } else if (order == "fixed") {
+        switchpoint_order = e_switch_point_order::FIXED;
+    } else if (order == "shuffled") {
+        switchpoint_order = e_switch_point_order::SHUFFLED;
     } else {
         archfpga_throw(__FILE__, __LINE__, "Unrecognized switchpoint order '%s'", order);
     }
@@ -328,19 +328,18 @@ static void parse_comma_separated_wire_points(const char* ch, std::vector<t_wire
 }
 
 static void parse_num_conns(std::string num_conns, t_wireconn_inf& wireconn) {
-    //num_conns is now interpretted as a formula and processed in build_switchblocks
+    // num_conns is now interpreted as a formula and processed in build_switchblocks
     wireconn.num_conns_formula = num_conns;
 }
 
-//set sides for a specific conn for custom switch block pattern
-static void set_switch_func_type(SBSideConnection& conn, const char* func_type) {
+static void set_switch_func_type(SBSideConnection& conn, std::string_view func_type) {
 
-    if (std::string(func_type).length() != 2) {
+    if (func_type.length() != 2) {
         archfpga_throw(__FILE__, __LINE__, "Custom switchblock func type must be 2 characters long: %s\n", func_type);
     }
 
     // Only valid sides are right, top, left, bottom, above and under
-    if (std::string(func_type).find_first_not_of("rtlbauRTLBAU") != std::string::npos) {
+    if (func_type.find_first_not_of("rtlbRTLB") != std::string::npos) {
         archfpga_throw(__FILE__, __LINE__, "Unknown direction specified: %s\n", func_type);
     }
 
@@ -352,12 +351,6 @@ static void set_switch_func_type(SBSideConnection& conn, const char* func_type)
         archfpga_throw(__FILE__, __LINE__, "Unknown permutation function specified, cannot go from side to same side: %s\n", func_type);
     }
 
-    // We don't allow specification of patterns that imply edges going over 2 or more layers
-    // (this doesn't seem electrically logical), so we disallow going from above/under to above/under.
-    if ((to_side == ABOVE || to_side == UNDER) && (from_side == ABOVE || from_side == UNDER)) {
-        archfpga_throw(__FILE__, __LINE__, "Unknown permutation function specified, cannot go from above/under to above/under: %s\n", func_type);
-    }
-
     conn.set_sides(from_side, to_side);
 }
 

diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h
@@ -32,7 +32,6 @@
 #include <unordered_map>
 #include <string>
 #include <map>
-#include <unordered_map>
 #include <limits>
 #include <unordered_set>
 
@@ -1686,28 +1685,6 @@ enum class SegResType {
 /// String versions of segment resource types
 constexpr std::array<const char*, static_cast<size_t>(SegResType::NUM_RES_TYPES)> RES_TYPE_STRING{"GCLK", "GENERAL"};
 
-/// Defines the type of switch block used in FPGA routing.
-enum e_switch_block_type {
-    /// If the type is SUBSET, I use a Xilinx-like switch block where track i in one channel always
-    /// connects to track i in other channels.
-    SUBSET,
-
-    /// If type is WILTON, I use a switch block where track i
-    /// does not always connect to track i in other channels.
-    /// See Steve Wilton, PhD Thesis, University of Toronto, 1996.
-    WILTON,
-
-    /// The UNIVERSAL switch block is from Y. W. Chang et al, TODAES, Jan. 1996, pp. 80 - 101.
-    UNIVERSAL,
-
-    /// The FULL switch block type allows for complete connectivity between tracks.
-    FULL,
-
-    /// A CUSTOM switch block has also been added which allows a user to describe custom permutation functions and connection patterns.
-    /// See comment at top of SRC/route/build_switchblocks.c
-    CUSTOM
-};
-
 enum e_Fc_type {
     ABSOLUTE,
     FRACTIONAL
@@ -1746,22 +1723,22 @@ struct t_segment_inf {
      * specified in the architecture file. If -1, this value was not set in the
      * architecture file and arch_wire_switch should be used for "DEC_DIR" wire segments.
      */
-    short arch_wire_switch_dec = -1;
+    short arch_wire_switch_dec = ARCH_FPGA_UNDEFINED_VAL;
 
     /**
      * @brief Same as arch_opin_switch but used only for decremental tracks if
      * it is specified in the architecture file. If -1, this value was not set in
      * the architecture file and arch_opin_switch should be used for "DEC_DIR" wire segments.
      */
-    short arch_opin_switch_dec = -1;
+    short arch_opin_switch_dec = ARCH_FPGA_UNDEFINED_VAL;
 
     /**
      * @brief Index of the switch type that connects output pins (OPINs) to this
      * segment from another die (layer). Note that this index is in relation to
      * the switches from the architecture file, not the expanded list of switches
      * that is built at the end of build_rr_graph.
      */
-    short arch_inter_die_switch = -1;
+    short arch_inter_die_switch = ARCH_FPGA_UNDEFINED_VAL;
 
     /**
      * @brief The fraction of logic blocks along its length to which this segment can connect.
@@ -1783,7 +1760,7 @@ struct t_segment_inf {
     ///  The capacitance of a routing track, per unit logic block length.
     float Cmetal;
 
-    enum e_directionality directionality;
+    e_directionality directionality;
 
     /**
      * @brief Defines what axis the segment is parallel to. See e_parallel_axis
@@ -1841,7 +1818,6 @@ inline bool operator==(const t_segment_inf& a, const t_segment_inf& b) {
            && a.length == b.length
            && a.arch_wire_switch == b.arch_wire_switch
            && a.arch_opin_switch == b.arch_opin_switch
-           && a.arch_inter_die_switch == b.arch_inter_die_switch
            && a.frac_cb == b.frac_cb
            && a.frac_sb == b.frac_sb
            && a.longline == b.longline

diff --git a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp
@@ -2328,7 +2328,7 @@ struct ArchReader {
         arch_->Chans.chan_y_dist.xpeak = 0;
         arch_->Chans.chan_y_dist.dc = 0;
         arch_->ipin_cblock_switch_name.push_back(std::string("generic"));
-        arch_->sb_type = WILTON;
+        arch_->sb_type = e_switch_block_type::WILTON;
         arch_->Fs = 3;
         default_fc_.specified = true;
         default_fc_.in_value_type = e_fc_value_type::FRACTIONAL;