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@tangxifan tangxifan commented Oct 27, 2025

Description

This is a follow-up PR on PR #3319

It adds the dedicated testcase to validate

  • When the destination sub tile is out of the range of subtiles in a tile, the direct connection builder should skip instead of aborting

The testcase will trigger another bug:

The clb_to_clb_directs relies on pin index to find the destination pin of subtiles. This is not reliable, which may cause wrong direct connections to be added.

Take the example of the testcases in this PR,

<direct name="cim_direct1" from_pin="cim8_16k.out[15:0]" to_pin="cim8_16k.d_in[31:16]" x_offset="0" y_offset="0" z_offset="-1"/>

The line expects to build direct connections from MULT[1] to RAM[0]. However, when checking if there are any connections required from MULT[2] to MULT[1], the current builder will mistakenly add an edge.
This is due to that the pin index of RAM[0] is always within the range of MULT[1] and MULT[2] (RAM has more pins than MULT).

+---------------+
|                         |
|    RAM[0]         |<-+----+
+---------------+    |        |
|    MULT[1]       |---+       |
+---------------+             |
|    MULT[2]       |--------+
+---------------+

This PR adds the port name to be checked when building the direct connection, to avoid such bug.

Related Issue

Motivation and Context

How Has This Been Tested?

Types of changes

  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool lang-cpp C/C++ code lang-netlist labels Oct 27, 2025
@tangxifan tangxifan requested a review from vaughnbetz October 27, 2025 09:13
@tangxifan
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@vaughnbetz This PR is ready for your review.

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A couple of minor suggestions in the comments.

clb_to_clb_directs[i].to_clb_type = physical_tile;

tile_port = find_tile_port_by_name(physical_tile, port_name);
// Cache the destination port name as the pin index is not enough to identify if the destination subtile is the one we want!!!
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Minor nit: we don't need the !!! at the end.
If there's something you want to emphasize about this test I think you'll have to explain it. But just adding !!! in comments will be a distraction.

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Understood. The exclamation has been removed.

}
}
VTR_ASSERT(to_sub_tile != nullptr);
/* Check if the to port is the one from the subtile, if not, pass as this is not the destination */
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Minor nit: we've moved to
// Use double slash for implementation comments

so if you can change to that style it would be good.

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Sure. I will keep this convention in future code changes.

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@vaughnbetz I have addressed the code comments. I merge this PR as CI is green. If you see any issue, I can address them in a follow-up PR.

@tangxifan tangxifan merged commit 78b4555 into master Oct 28, 2025
30 checks passed
@tangxifan tangxifan deleted the xt_direct_inport_double_check branch October 28, 2025 02:50
@tangxifan tangxifan restored the xt_direct_inport_double_check branch October 28, 2025 02:50
@tangxifan tangxifan deleted the xt_direct_inport_double_check branch October 28, 2025 02:50
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3 participants