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CP-308875: set Xen PCI MMIO BAR to WB #6591

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Merged
merged 1 commit into from
Jul 15, 2025
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CP-308875: set Xen PCI MMIO BAR to WB #6591

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9 changes: 8 additions & 1 deletion ocaml/xenopsd/lib/xenopsd.ml
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Expand Up @@ -49,7 +49,14 @@ let default_vbd_backend_kind = ref "vbd"

let ca_140252_workaround = ref false

let xen_platform_pci_bar_uc = ref true
(* Optimize performance: set MTRR WB attribute on Xen PCI MMIO BAR.
This is useful for AMD, and mostly a noop on Intel (which achieves a similar
effect using Intel-only features in Xen)
Comment on lines +53 to +54
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The part in brackets is going to go stale quickly. In order to support encrypted memory (and later, encrypted VMs), we're going to have to stop using iPAT on Intel, at which point Intel will become like AMD and this control will be relevant.

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ok, so doing this uniformly now on both Intel and AMD actually future proofs us against that. You can then change the Intel side from iPAT in Xen without further toolstack changes?

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correct


Turning on WB is done by disabling UC:
UnCached=false -> WriteBack=true
*)
let xen_platform_pci_bar_uc = ref false

let action_after_qemu_crash = ref None

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4 changes: 3 additions & 1 deletion ocaml/xenopsd/xenopsd.conf
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Expand Up @@ -113,4 +113,6 @@ disable-logging-for=http tracing tracing_export
# by grant tables is mapped as Uncached (UC, the default) or WriteBack
# (WB, the workaround). WB mapping could improve performance of devices
# using grant tables. This is useful on AMD platform only.
# xen-platform-pci-bar-uc=true
# On Intel a similar effect is already achieved with iPAT in Xen,
# but setting this to 0 works on Intel too.
# xen-platform-pci-bar-uc=false
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