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axi_dmac: Default to 64 bit addressing #1879

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axi_dmac: Default to 64 bit addressing #1879

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4 changes: 2 additions & 2 deletions docs/regmap/adi_regmap_dmac.txt
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Expand Up @@ -9,7 +9,7 @@ ENDTITLE
REG
0x000
VERSION
Version of the peripheral. Follows semantic versioning. Current version 4.05.64.
Version of the peripheral. Follows semantic versioning. Current version 4.05.65.
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Do we want this as a patch? Doesn't it break stuff for old boards that only have 32 bits addresses?

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@podgori podgori Aug 20, 2025 •
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The old boards shouldn't be impacted, since the default value of 64 will be overwritten by the post_propagate procedure, which will decrease it to 32 bits or less.

ENDREG

FIELD
Expand All @@ -25,7 +25,7 @@ RO
ENDFIELD

FIELD
[7:0] 0x00000064
[7:0] 0x00000065
VERSION_PATCH
RO
ENDFIELD
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4 changes: 2 additions & 2 deletions library/axi_dmac/address_generator.v
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -39,7 +39,7 @@ module address_generator #(

parameter ID_WIDTH = 3,
parameter DMA_DATA_WIDTH = 64,
parameter DMA_ADDR_WIDTH = 32,
parameter DMA_ADDR_WIDTH = 64,
parameter BEATS_PER_BURST_WIDTH = 4,
parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8),
parameter LENGTH_WIDTH = 8,
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4 changes: 2 additions & 2 deletions library/axi_dmac/axi_dmac.v
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -60,7 +60,7 @@ module axi_dmac #(
parameter DMA_AXI_PROTOCOL_SG = 0,
parameter DMA_TYPE_DEST = 0,
parameter DMA_TYPE_SRC = 2,
parameter DMA_AXI_ADDR_WIDTH = 32,
parameter DMA_AXI_ADDR_WIDTH = 64,
parameter MAX_BYTES_PER_BURST = 128,
parameter FIFO_SIZE = 8, // In bursts
parameter AXI_ID_WIDTH_SRC = 1,
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4 changes: 2 additions & 2 deletions library/axi_dmac/axi_dmac_framelock.v
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2024-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -34,7 +34,7 @@
// ***************************************************************************

module axi_dmac_framelock #(
parameter DMA_AXI_ADDR_WIDTH = 32,
parameter DMA_AXI_ADDR_WIDTH = 64,
parameter BYTES_PER_BEAT_WIDTH_DEST = 3,
parameter BYTES_PER_BEAT_WIDTH_SRC = 3,
parameter FRAMELOCK_MODE = 0, // 0 - MM writer ; 1 - MM reader
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6 changes: 3 additions & 3 deletions library/axi_dmac/axi_dmac_regmap.v
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -44,7 +44,7 @@ module axi_dmac_regmap #(
parameter BYTES_PER_BURST_WIDTH = 7,
parameter DMA_TYPE_DEST = 0,
parameter DMA_TYPE_SRC = 2,
parameter DMA_AXI_ADDR_WIDTH = 32,
parameter DMA_AXI_ADDR_WIDTH = 64,
parameter DMA_LENGTH_WIDTH = 24,
parameter DMA_LENGTH_ALIGN = 3,
parameter DMA_CYCLIC = 0,
Expand Down Expand Up @@ -147,7 +147,7 @@ module axi_dmac_regmap #(
input [31:0] dbg_ids1
);

localparam PCORE_VERSION = 'h00040564;
localparam PCORE_VERSION = 'h00040565;
localparam HAS_ADDR_HIGH = DMA_AXI_ADDR_WIDTH > 32;
localparam ADDR_LOW_MSB = HAS_ADDR_HIGH ? 31 : DMA_AXI_ADDR_WIDTH-1;

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4 changes: 2 additions & 2 deletions library/axi_dmac/axi_dmac_regmap_request.v
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2018-2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2018-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -41,7 +41,7 @@ module axi_dmac_regmap_request #(
parameter BYTES_PER_BEAT_WIDTH_SRC = 1,
parameter BYTES_PER_BEAT_WIDTH_SG = 1,
parameter BYTES_PER_BURST_WIDTH = 7,
parameter DMA_AXI_ADDR_WIDTH = 32,
parameter DMA_AXI_ADDR_WIDTH = 64,
parameter DMA_LENGTH_WIDTH = 24,
parameter DMA_LENGTH_ALIGN = 3,
parameter DMA_CYCLIC = 0,
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4 changes: 2 additions & 2 deletions library/axi_dmac/axi_dmac_transfer.v
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -46,7 +46,7 @@ module axi_dmac_transfer #(
parameter BYTES_PER_BEAT_WIDTH_SG = $clog2(DMA_DATA_WIDTH_SG/8),
parameter DMA_TYPE_DEST = 0,
parameter DMA_TYPE_SRC = 2,
parameter DMA_AXI_ADDR_WIDTH = 32,
parameter DMA_AXI_ADDR_WIDTH = 64,
parameter DMA_2D_TRANSFER = 0,
parameter DMA_2D_TLAST_MODE = 0,
parameter DMA_SG_TRANSFER = 0,
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4 changes: 2 additions & 2 deletions library/axi_dmac/dest_axi_mm.v
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -39,7 +39,7 @@ module dest_axi_mm #(

parameter ID_WIDTH = 3,
parameter DMA_DATA_WIDTH = 64,
parameter DMA_ADDR_WIDTH = 32,
parameter DMA_ADDR_WIDTH = 64,
parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8),
parameter BEATS_PER_BURST_WIDTH = 4,
parameter MAX_BYTES_PER_BURST = 128,
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4 changes: 2 additions & 2 deletions library/axi_dmac/dmac_2d_transfer.v
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -38,7 +38,7 @@
module dmac_2d_transfer #(

parameter DMA_2D_TLAST_MODE = 0, // 0 - End of Frame; 1 - End of Line
parameter DMA_AXI_ADDR_WIDTH = 32,
parameter DMA_AXI_ADDR_WIDTH = 64,
parameter DMA_LENGTH_WIDTH = 24,
parameter BYTES_PER_BURST_WIDTH = 7,
parameter BYTES_PER_BEAT_WIDTH_SRC = 3,
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4 changes: 2 additions & 2 deletions library/axi_dmac/dmac_sg.v
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2023-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -36,7 +36,7 @@
`timescale 1ns/100ps

module dmac_sg #(
parameter DMA_AXI_ADDR_WIDTH = 32,
parameter DMA_AXI_ADDR_WIDTH = 64,
parameter DMA_DATA_WIDTH = 64,
parameter DMA_LENGTH_WIDTH = 24,
parameter AXI_LENGTH_WIDTH = 8,
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4 changes: 2 additions & 2 deletions library/axi_dmac/request_arb.v
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -44,7 +44,7 @@ module request_arb #(
parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(DMA_DATA_WIDTH_SRC/8),
parameter DMA_TYPE_DEST = 0,
parameter DMA_TYPE_SRC = 2,
parameter DMA_AXI_ADDR_WIDTH = 32,
parameter DMA_AXI_ADDR_WIDTH = 64,
parameter ASYNC_CLK_REQ_SRC = 1,
parameter ASYNC_CLK_SRC_DEST = 1,
parameter ASYNC_CLK_DEST_REQ = 1,
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4 changes: 2 additions & 2 deletions library/axi_dmac/src_axi_mm.v
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -39,7 +39,7 @@ module src_axi_mm #(

parameter ID_WIDTH = 3,
parameter DMA_DATA_WIDTH = 64,
parameter DMA_ADDR_WIDTH = 32,
parameter DMA_ADDR_WIDTH = 64,
parameter BYTES_PER_BEAT_WIDTH = 3,
parameter BEATS_PER_BURST_WIDTH = 4,
parameter AXI_LENGTH_WIDTH = 8,
Expand Down