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@podgori podgori commented Aug 14, 2025

This commit increases the maximum address width of the DMA AXI interfaces to 64 to enable accessing the upper DDR memory regions of the 64 bit address spaces.

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)
  • Documentation

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

This commit increases the maximum address width of the DMA AXI interfaces to 64
to enable accessing the upper DDR memory regions of the 64 bit address spaces.

Signed-off-by: Ionut Podgoreanu <[email protected]>
@@ -9,7 +9,7 @@ ENDTITLE
REG
0x000
VERSION
Version of the peripheral. Follows semantic versioning. Current version 4.05.64.
Version of the peripheral. Follows semantic versioning. Current version 4.05.65.
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Do we want this as a patch? Doesn't it break stuff for old boards that only have 32 bits addresses?

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@podgori podgori Aug 20, 2025

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The old boards shouldn't be impacted, since the default value of 64 will be overwritten by the post_propagate procedure, which will decrease it to 32 bits or less.

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2 participants