library/spi_engine, library/util_sigma_delta_spi: remove spi active

docs/library/spi_engine/spi_engine_execution.rst

@@ -52,9 +52,6 @@ Signal and Interface Pins
      - All other signals are synchronous to this clock.
    * - resetn
      - Resets the internal state machine of the core.
-   * - active
-     - Indicates whether the peripheral is currently active and processing
-       commands.
    * - ctrl
      - :ref:`spi_engine control-interface` subordinate.
        SPI Engine Control stream that contains commands and data for the
@@ -72,8 +69,6 @@ SPI Engine command stream into low-level SPI bus access.
 
 Communication with a command stream generator happens via the ``ctrl``
 interface and the low-level SPI access is handled on the ``spi`` interface.
-The ``active`` signal is asserted as long as the peripheral is busy executing
-incoming commands.
 
 Internally the SPI Engine execution module consists of an instruction encoder
 that translates the incoming commands into an internal control signal, a

docs/library/util_sigma_delta_spi/index.rst

@@ -58,8 +58,7 @@ the ADC, or it can be connected to a HDL block, like the
 transaction to read the converted signal.
 
 The data ready condition is only detected if the chip-select signal (which is
-connected to the converter) is asserted and the ``spi_active`` signal is
-de-asserted and both signals have been in that state for **at least**
+connected to the converter) is asserted has been in that state for **at least**
 ``IDLE_TIMEOUT`` clock cycles.
 
 The timeout is used to avoid spurious signal detection and the ``IDLE_TIMEOUT``

library/spi_engine/spi_engine_execution/spi_engine_execution.v

@@ -49,8 +49,6 @@ module spi_engine_execution #(
   input clk,
   input resetn,
 
-  output reg active,
-
   output cmd_ready,
   input cmd_valid,
   input [15:0] cmd,
@@ -227,17 +225,6 @@ module spi_engine_execution #(
      cmd_d1 <= cmd;
   end
 
-  always @(posedge clk) begin
-    if (resetn == 1'b0) begin
-      active <= 1'b0;
-    end else begin
-      if (exec_cmd == 1'b1)
-        active <= 1'b1;
-      else if (sync_ready == 1'b1 && sync_valid == 1'b1)
-        active <= 1'b0;
-    end
-  end
-
   // Load the interface configurations from the 'Configuration Write'
   // instruction
   always @(posedge clk) begin

library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl

@@ -34,8 +34,6 @@ proc p_elaboration {} {
   ad_interface clock   clk     input 1
   ad_interface reset   resetn  input 1 if_clk
 
-  ad_interface signal active output 1
-
   # command interface
 
   add_interface cmd axi4stream end

library/util_sigma_delta_spi/util_sigma_delta_spi.v

@@ -44,8 +44,6 @@ module util_sigma_delta_spi #(
   input clk,
   input resetn,
 
-  input spi_active,
-
   input s_sclk,
   input s_sdo,
   input s_sdo_t,
@@ -62,15 +60,15 @@ module util_sigma_delta_spi #(
 );
 
  /*
-  * For converters from the ADI SigmaDelta family the data ready interrupt signal
-  * uses the same physical wire as the the DOUT signal for the SPI bus. This
-  * module extracts the data ready signal from the SPI bus and makes sure to
-  * suppress false positives. The data ready signal is indicated by the converter
-  * by pulling DOUT low. This will only happen if the CS pin for the converter is
-  * low and no SPI transfer is active. There is a small delay between the end of
-  * the SPI transfer and the point where the converter starts to indicate the
-  * data ready signal. IDLE_TIMEOUT allows to specify the amount of clock cycles
-  * the bus needs to be idle before the data ready signal is detected.
+  * For converters from the ADI SigmaDelta family the data ready interrupt
+  * signal uses the same physical wire as the the DOUT signal for the SPI bus.
+  * This module extracts the data ready signal from the SPI bus and makes sure
+  * to suppress false positives. The data ready signal is indicated by the
+  * converter by pulling DOUT low. This will only happen if the CS pin for the
+  * converter is low. There is a small delay between the end of the SPI transfer
+  * and the point where the converter starts to indicate the data ready signal.
+  * IDLE_TIMEOUT allows to specify the amount of clock cycles the bus needs to
+  * be idle before the data ready signal is detected.
   */
 
   assign m_sclk = s_sclk;
@@ -86,7 +84,7 @@ module util_sigma_delta_spi #(
     if (resetn == 1'b0) begin
       counter <= IDLE_TIMEOUT;
     end else begin
-      if (s_cs[CS_PIN] == 1'b0 && spi_active == 1'b0) begin
+      if (s_cs[CS_PIN] == 1'b0) begin
         if (counter != 'h00)
           counter <= counter - 1'b1;
       end else begin

library/util_sigma_delta_spi/util_sigma_delta_spi_hw.tcl

@@ -30,7 +30,6 @@ proc p_elaboration {} {
   ad_interface clock clk    input 1
   ad_interface reset resetn input 1 if_clk
 
-  ad_interface signal spi_active input 1 active
   ad_interface signal data_ready output 1 if_pwm
 
   ad_interface clock s_sclk   input 1 sclk

projects/ad411x_ad717x/common/ad411x_ad717x_asdz_qsys.tcl

@@ -78,7 +78,6 @@ add_connection spi_engine_execution_0.if_sdi util_sigma_delta_spi.if_s_sdi
 add_connection spi_engine_execution_0.if_sdo util_sigma_delta_spi.if_s_sdo
 add_connection spi_engine_execution_0.if_sdo_t util_sigma_delta_spi.if_s_sdo_t
 add_connection spi_engine_offload_0.if_trigger util_sigma_delta_spi.if_data_ready
-add_connection spi_engine_execution_0.if_active util_sigma_delta_spi.if_spi_active
 
 # add_connection axi_spi_engine_0.
 

projects/cn0363/common/cn0363_bd.tcl

@@ -70,7 +70,6 @@ ad_connect util_sigma_delta_spi/resetn $hier_spi_engine/resetn
 
 ad_connect $hier_spi_engine/m_spi util_sigma_delta_spi/s_spi
 ad_connect util_sigma_delta_spi/data_ready $hier_spi_engine/trigger
-ad_connect $hier_spi_engine/${hier_spi_engine}_execution/active util_sigma_delta_spi/spi_active
 ad_connect util_sigma_delta_spi/m_spi spi
 
 ad_ip_instance c_counter_binary phase_gen