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1. fifo_buffer_sky130 fifo_buffer_sky130 Public

   Physical design of a synchronous FIFO using OpenROAD

   Verilog

2. FPGA-Edge-Detector-with-AXI-Video-Pipeline FPGA-Edge-Detector-with-AXI-Video-Pipeline Public

   This project implements a real-time edge detection system on an FPGA using a custom Sobel filter, integrated into an AXI4-Stream video processing pipeline.