Process Node: Sky130 (130nm)
Target Frequency: 100MHz
Library: sky130_fd_sc_hd
This repository documents the physical implementation of a synchronous FIFO buffer using the OpenROAD flow. The design achieves a high-density logic placement of approximately 90% while meeting all timing constraints for a 100MHz clock period.
Data extracted from final sign-off reports (6_finish.rpt and 6_final.power.rpt):
| Parameter | Specification | Verification Status |
|---|---|---|
| Clock Frequency | 100 MHz (10.00 ns period) | Passed |
| Setup Slack | 3.69 ns | Met |
| Hold Slack | 3.02 ns | Met |
| Total Cell Count | 6,216 cells | Verified |
| Sequential Cells | 1,072 DFFs | Verified |
| Total Power | 13.4 mW | Verified |
| Total Area | 62,167.12 µm² | Verified |
| Max IR-Drop | 0.01% | Verified |
The design utilizes a high-density placement strategy to minimize wire length and parasitic capacitance. Final routing was completed with zero DRC violations.
Figure 1: Core placement density heatmap showing logic distribution.
The clock distribution network consists of 131 buffers and 56 inverters, resulting in 0.000ns of clock skew.
Figure 2: Global clock net tracing and buffer distribution.
The maximum observed IR-drop is 0.01%, ensuring reliable switching of the 1,072 sequential elements.
Figure 3: IR-drop visualization across the core area.
Klayout design of a d-flip-flop cell
Figure 4: Cell layout of a d flip flop.
Test bench of fifo buffer
Figure 5: Test bench created in Vivado.
- /rtl: Verilog source code and functional testbench.
- /constraint: Physical design configuration (
config.mk) and SDC constraints (updated_clks.sdc). - /gds: Manufacturing files (GDSII, gate-level netlist, SPEF parasitics).
- /reports: Sign-off reports for timing, power, and physical verification.
- /media: Physical design visualizations and heatmaps.
Future development involves integrating this FIFO into a UART protocol subsystem to facilitate asynchronous serial data buffering.