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syntax-checks.yaml
1,894 workflow runs
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Verilog: {} and {{}} do not need parentheses Syntactic checks #1213: Pull request #671 opened by kroening
2m 49s paren-concat
paren-concat
2m 49s
Verilog: typechecking for relations Syntactic checks #1212: Pull request #667 synchronize by kroening
1m 18s typecheck_relation
typecheck_relation
1m 18s
Verilog: size-cast expression with Boolean operand Syntactic checks #1211: Pull request #670 opened by kroening
1m 16s size-cast-on-bool
size-cast-on-bool
1m 16s
Verilog: typechecking for relations Syntactic checks #1210: Pull request #667 synchronize by kroening
1m 31s typecheck_relation
typecheck_relation
1m 31s
Verilog: default aval/bval lowering Syntactic checks #1209: Pull request #668 opened by kroening
1m 18s default_aval_bval_encoding
default_aval_bval_encoding
1m 18s
Verilog: typechecking for relations Syntactic checks #1208: Pull request #667 opened by kroening
1m 16s typecheck_relation
typecheck_relation
1m 16s
SystemVerilog: wildcard equality and inequality Syntactic checks #1207: Pull request #661 synchronize by kroening
1m 20s verilog_wildcard_equality
verilog_wildcard_equality
1m 20s
Verilog: fix for signed constants Syntactic checks #1206: Pull request #660 synchronize by kroening
1m 15s fix-signed-constants
fix-signed-constants
1m 15s
Verilog: fix for signed constants Syntactic checks #1205: Pull request #660 synchronize by kroening
1m 17s fix-signed-constants
fix-signed-constants
1m 17s
Verilog: fix for signed constants Syntactic checks #1204: Pull request #660 synchronize by kroening
1m 21s fix-signed-constants
fix-signed-constants
1m 21s
Verilog: constant output now includes signedness and width Syntactic checks #1203: Pull request #662 synchronize by kroening
1m 18s verilog-constant-output
verilog-constant-output
1m 18s
Verilog: constant output now includes signedness and width Syntactic checks #1202: Pull request #662 synchronize by kroening
1m 18s verilog-constant-output
verilog-constant-output
1m 18s
Verilog: error on wire redeclaration Syntactic checks #1201: Pull request #666 opened by kroening
1m 23s wire-redeclaration
wire-redeclaration
1m 23s
SVA: implement indexed nexttime Syntactic checks #1200: Pull request #665 synchronize by kroening
1m 23s indexed_nexttime
indexed_nexttime
1m 23s
SVA: implement indexed nexttime Syntactic checks #1199: Pull request #665 synchronize by kroening
1m 18s indexed_nexttime
indexed_nexttime
1m 18s
SVA: implement indexed nexttime Syntactic checks #1198: Pull request #665 opened by kroening
1m 16s indexed_nexttime
indexed_nexttime
1m 16s
Verilog: KNOWNBUG test for negation Syntactic checks #1197: Pull request #663 synchronize by kroening
1m 24s negation1.desc
negation1.desc
1m 24s
Verilog: KNOWNBUG test for negation Syntactic checks #1196: Pull request #663 synchronize by kroening
1m 17s negation1.desc
negation1.desc
1m 17s
Verilog: KNOWNBUG test for power operator Syntactic checks #1195: Pull request #664 synchronize by kroening
1m 17s power1
power1
1m 17s
Verilog: KNOWNBUG test for power operator Syntactic checks #1194: Pull request #664 opened by kroening
1m 16s power1
power1
1m 16s
Verilog: KNOWNBUG test for negation Syntactic checks #1193: Pull request #663 opened by kroening
1m 21s negation1.desc
negation1.desc
1m 21s
SystemVerilog: wildcard equality and inequality Syntactic checks #1192: Pull request #661 synchronize by kroening
1m 20s verilog_wildcard_equality
verilog_wildcard_equality
1m 20s
SystemVerilog: wildcard equality and inequality Syntactic checks #1191: Pull request #661 synchronize by kroening
1m 19s verilog_wildcard_equality
verilog_wildcard_equality
1m 19s
Verilog: create_module now returns verilog_module_sourcet Syntactic checks #1190: Pull request #648 synchronize by kroening
1m 21s create_module
create_module
1m 21s
Verilog: fix for signed constants Syntactic checks #1189: Pull request #660 synchronize by kroening
1m 16s fix-signed-constants
fix-signed-constants
1m 16s
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