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syntax-checks.yaml
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SystemVerilog: wildcard equality and inequality Syntactic checks #1183: Pull request #661 opened by kroening
1m 16s verilog_wildcard_equality
verilog_wildcard_equality
1m 16s
aval/bval lowering for Verilog logical equality Syntactic checks #1182: Pull request #656 synchronize by kroening
1m 20s verilog_equality_lowering
verilog_equality_lowering
1m 20s
aval/bval lowering for Verilog logical equality Syntactic checks #1181: Pull request #656 synchronize by kroening
1m 14s verilog_equality_lowering
verilog_equality_lowering
1m 14s
SystemVeriliog: KNOWNBUG test for nested modules Syntactic checks #1180: Pull request #604 synchronize by kroening
1m 14s nested_modules
nested_modules
1m 14s
Verilog: fix for signed constants Syntactic checks #1179: Pull request #660 opened by kroening
1m 21s fix-signed-constants
fix-signed-constants
1m 21s
KNOWNBUG test for SystemVerilog wildcard equality Syntactic checks #1178: Pull request #657 opened by kroening
1m 21s wildcard_equality1
wildcard_equality1
1m 21s
aval/bval lowering for Verilog logical equality Syntactic checks #1177: Pull request #656 synchronize by kroening
1m 14s verilog_equality_lowering
verilog_equality_lowering
1m 14s
aval/bval lowering for Verilog logical equality Syntactic checks #1176: Pull request #656 opened by kroening
1m 19s verilog_equality_lowering
verilog_equality_lowering
1m 19s
Verilog: KNOWNBUG test for signed base 2 literal Syntactic checks #1175: Pull request #655 opened by kroening
1m 20s signed2
signed2
1m 20s
move signed1 test Syntactic checks #1174: Pull request #654 opened by kroening
1m 17s signed1-1
signed1-1
1m 17s
posedge_vector test should be CORE Syntactic checks #1173: Pull request #653 opened by kroening
1m 15s posedge_vector2
posedge_vector2
1m 15s
Mark k-induction test as CORE Syntactic checks #1172: Pull request #652 synchronize by kroening
1m 22s k-induction5.k-3.desc
k-induction5.k-3.desc
1m 22s
Mark k-induction test as CORE Syntactic checks #1171: Pull request #652 opened by kroening
1m 21s k-induction5.k-3.desc
k-induction5.k-3.desc
1m 21s
Verilog: create_module now returns verilog_module_sourcet Syntactic checks #1170: Pull request #648 synchronize by kroening
1m 19s create_module
create_module
1m 19s
introduce property_checker_resultt Syntactic checks #1169: Pull request #651 synchronize by kroening
1m 18s property_checker_resultt
property_checker_resultt
1m 18s
introduce property_checker_resultt Syntactic checks #1168: Pull request #651 synchronize by kroening
1m 22s property_checker_resultt
property_checker_resultt
1m 22s
introduce property_checker_resultt Syntactic checks #1167: Pull request #651 synchronize by kroening
1m 16s property_checker_resultt
property_checker_resultt
1m 16s
introduce property_checker_resultt Syntactic checks #1166: Pull request #651 synchronize by kroening
1m 16s property_checker_resultt
property_checker_resultt
1m 16s
introduce property_checker_resultt Syntactic checks #1165: Pull request #651 opened by kroening
1m 24s property_checker_resultt
property_checker_resultt
1m 24s
Move k-induction invocation Syntactic checks #1164: Pull request #650 opened by kroening
3m 4s move_k_induction
move_k_induction
3m 4s
Move BDD engine invocation Syntactic checks #1163: Pull request #649 synchronize by kroening
1m 15s move_bdd
move_bdd
1m 15s
Move BDD engine invocation Syntactic checks #1162: Pull request #649 synchronize by kroening
1m 18s move_bdd
move_bdd
1m 18s
Move BDD engine invocation Syntactic checks #1161: Pull request #649 opened by kroening
1m 15s move_bdd
move_bdd
1m 15s
SystemVeriliog: KNOWNBUG test for nested modules Syntactic checks #1160: Pull request #604 synchronize by kroening
1m 20s nested_modules
nested_modules
1m 20s
Verilog: create_module now returns verilog_module_sourcet Syntactic checks #1159: Pull request #648 opened by kroening
1m 18s create_module
create_module
1m 18s
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