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Verilog: fix synthesis for assignment to indexed part select #637

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Merged
merged 2 commits into from
Aug 16, 2024
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Verilog: fix synthesis for assignment to indexed part select #637

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4467d38
Verilog: KNOWNBUG test for assignment to indexed part select
kroening Aug 14, 2024
862bdf7
SystemVerilog: fix for synthesis for indexed part select
kroening Aug 14, 2024
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9 changes: 9 additions & 0 deletions regression/verilog/part-select/indexed-part-select5.desc
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Original file line number Diff line number Diff line change
@@ -0,0 +1,9 @@
KNOWNBUG
indexed-part-select5.sv
--bound 0
^EXIT=0$
^SIGNAL=0$
--
^warning: ignoring
--
This yields invalid SMT-LIB ("invalid extract application").
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For that to materialise, wouldn't also some --smt command line be required?

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We do run all tests both with the flattening backend and with Z3.

14 changes: 14 additions & 0 deletions regression/verilog/part-select/indexed-part-select5.sv
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module main(input my_input);

bit [7:0] some_wire;

always @my_input begin
some_wire[0 +: 2] = 'b01;
some_wire[2 +: 2] = 'b01;
some_wire[4 +: 2] = 'b01;
some_wire[6 +: 2] = 'b01;
end

p0: assert final (some_wire == 'b01_01_01_01);

endmodule