Verilog: fix synthesis for assignment to indexed part select #637
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kroening
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This adds a test for an assignment to an indexed part select with constant indices. The test yields invalid SMT-LIB.
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tautschnig
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Aug 14, 2024
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| ^warning: ignoring | ||
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| This yields invalid SMT-LIB ("invalid extract application"). |
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For that to materialise, wouldn't also some --smt command line be required?
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We do run all tests both with the flattening backend and with Z3.
This fixes an off-by-one error in the synthesis for indexed part select expressions.
kroening
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tautschnig
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Romy15200
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Aug 19, 2025
Verilog: fix synthesis for assignment to indexed part select
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