feature: Add RoundRobin SP_TIMESLICE switch policy

[thiagomoraisee]

Summary

This pull request introduces a new arbitration switch policy named SP_TIMESLICE to the RoundRobin module in migen.genlib.roundrobin.

Motivation

Consider an arbiter that grants access to a shared book for two writers. One writer just wants to sign their name, while the other plans to write an entire chapter. The question is: "Once the chapter writer starts using the book, is it fair for the signer to wait until the entire chapter is finished, just to sign their name?".
This illustrates a common problem in resource arbitration where long or variable transactions from one master can block others indefinitely, or for a very long time. The SP_TIMESLICE policy addresses this by limiting how long a master can hold the grant (max_cycles), ensuring that long transactions don’t block others, improving the resources allocation and avoiding deadlocks in shared-resource systems.

Main Changes

• migen/genlib/roundrobin.py:

  • Added SP_TIMESLICE constant and modified the RoundRobin module to handle this new policy.
  • Introduced a new signal:
    • transok: Input signal (one per master) indicating whether the last transaction was successfully completed. It prevents premature switching in the middle of an active transaction;

• migen/test/test_roundrobin.py:

  • Add SP_TIMESLICE unit test

• migen/genlib/support.py:

  • Pass optional **kwargs to SimCase.run_with() method, enabling the VCD generation directly from this method.

Tests

A new test case, test_grant_switch, was added to test_roundrobin.py to validate the SP_TIMESLICE behavior. The test ensures that grant switching occurs when the internal counter reaches max_cycles and no transaction is currently in progress. To run the test, execute the command below from the migen/migen/test directory.

python3 -m unittest test_roundrobin.py

Evidences

Evidence 1: VCD of unit test

As shown in the image below, the grant switches when max_cycles is reached and no transaction is in progress. This VCD waveform was generated using SimCase.run_with() with the vcd_name parameter set accordingly. The snapshot displays the relevant signals in the GTKWave interface.

Evidence 2: Vivado FPGA validation

The image below shows the waveform from the Vivado simulator using the RoundRobin arbiter with the implemented SP_TIMESLICE policy. In this simulation, two Wishbone masters requests read/write access at the same time to a shared slave memory. The masters' requests can be seen by the CYC and STB signals, while the slave's ACK signal is connected to the arbiter's transok input. The equivalent Verilog design was also implemented and validated on a Xilinx Artix-7 FPGA.

Checklist

• Code changes compile without errors;
• Feature covered by unit tests;
• Follows Migen code style and conventions;
• Backwards-compatible;