feature: Add RoundRobin SP_TIMESLICE switch policy

migen/genlib/roundrobin.py

@@ -1,18 +1,22 @@
 from migen.fhdl.structure import *
 from migen.fhdl.module import Module
 
-
-(SP_WITHDRAW, SP_CE) = range(2)
-
+(SP_WITHDRAW, SP_CE, SP_TIMESLICE) = range(3)
 
 class RoundRobin(Module):
-    def __init__(self, n, switch_policy=SP_WITHDRAW):
+    def __init__(self, n, switch_policy=SP_WITHDRAW, max_cycles=64):
         self.request = Signal(n)
         self.grant = Signal(max=max(2, n))
         self.switch_policy = switch_policy
+
         if self.switch_policy == SP_CE:
             self.ce = Signal()
 
+        if self.switch_policy == SP_TIMESLICE:
+            self.transok = Signal(n)
+            self.max_cycles = max_cycles
+            self.counter = Signal(max=max_cycles + 1)
+
         ###
 
         if n > 1:
@@ -23,19 +27,37 @@ def __init__(self, n, switch_policy=SP_WITHDRAW):
                     t = j % n
                     switch = [
                         If(self.request[t],
-                            self.grant.eq(t)
+                           self.grant.eq(t)
                         ).Else(
                             *switch
                         )
                     ]
+
                 if self.switch_policy == SP_WITHDRAW:
                     case = [If(~self.request[i], *switch)]
+
+                elif self.switch_policy == SP_TIMESLICE:
+                    case = [
+                        If((~self.request[i]) | ((self.counter >= self.max_cycles) & self.transok[i]),
+                           self.counter.eq(0),  # reset counter when switching
+                           *switch
+                        ).Else(
+                           self.counter.eq(self.counter + 1)
+                        )
+                    ]
+
                 else:
-                    case = switch
+                    case = switch  # SP_CE
+
                 cases[i] = case
+
             statement = Case(self.grant, cases)
+
             if self.switch_policy == SP_CE:
                 statement = If(self.ce, statement)
+
             self.sync += statement
+
         else:
             self.comb += self.grant.eq(0)
+

migen/test/support.py

@@ -9,5 +9,5 @@ def setUp(self, *args, **kwargs):
     def test_to_verilog(self):
         verilog.convert(self.tb)
 
-    def run_with(self, generator):
-        run_simulation(self.tb, generator)
+    def run_with(self, generator, **kwargs):
+        run_simulation(self.tb, generator, **kwargs)

migen/test/test_roundrobin.py

@@ -0,0 +1,44 @@
+import unittest
+from itertools import count
+
+from migen import *
+from migen.genlib.roundrobin import RoundRobin, SP_TIMESLICE
+from migen.test.support import SimCase
+
+class RoundRobinCase(SimCase, unittest.TestCase):
+    class TestBench(Module):
+        def __init__(self):
+            self.submodules.dut = RoundRobin(n=2, switch_policy=SP_TIMESLICE, max_cycles=8)
+
+    def test_grant_switch(self, vcd=True):
+        def gen():
+            expected_grants = [0]*10 + [1]*10 + [0]*10
+            observed_grants = []
+            for cycle in count():
+                if cycle == 0:
+                    yield self.tb.dut.request[0].eq(1)
+                    yield self.tb.dut.request[1].eq(1)
+                    yield
+                elif cycle == 31:
+                    break
+                else:
+                    grant = (yield self.tb.dut.grant)
+                    transok = (yield self.tb.dut.transok)
+
+                    observed_grants.append(grant)
+                    if(yield self.tb.dut.transok[grant]):
+                        self.assertLessEqual((yield self.tb.dut.counter), 9)
+
+                    if(yield self.tb.dut.transok[grant]):
+                        yield self.tb.dut.transok[grant].eq(0)
+                    else:
+                        yield self.tb.dut.transok[grant].eq(1)
+                    yield
+
+            self.assertEqual(observed_grants, expected_grants)
+
+
+        if vcd:
+            self.run_with(gen(), vcd_name='roundrobin.vcd')
+        else:
+            self.run_with(gen())