8329077: C2 SuperWord: Add MoveD2L, MoveL2D, MoveF2I, MoveI2F #26457

galderz · 2025-07-24T10:29:15Z

I've added support to vectorize MoveD2L, MoveL2D, MoveF2I and MoveI2F nodes. The implementation follows a similar pattern to what is done with conversion (Conv*) nodes. The tests in TestCompatibleUseDefTypeSize have been updated with the new expectations.

Also added a JMH benchmark which measures throughput (the higher the number the better) for methods that exercise these nodes. On darwin/aarch64 it shows:

Benchmark                                (seed)  (size)   Mode  Cnt      Base      Patch   Units   Diff
VectorBitConversion.doubleToLongBits          0    2048  thrpt    8  1168.782   1157.717  ops/ms    -1%
VectorBitConversion.doubleToRawLongBits       0    2048  thrpt    8  3999.387   7353.936  ops/ms   +83%
VectorBitConversion.floatToIntBits            0    2048  thrpt    8  1200.338   1188.206  ops/ms    -1%
VectorBitConversion.floatToRawIntBits         0    2048  thrpt    8  4058.248  14792.474  ops/ms  +264%
VectorBitConversion.intBitsToFloat            0    2048  thrpt    8  3050.313  14984.246  ops/ms  +391%
VectorBitConversion.longBitsToDouble          0    2048  thrpt    8  3022.691   7379.360  ops/ms  +144%

The improvements observed are a result of vectorization. The lack of vectorization in doubleToLongBits and floatToIntBits demonstrates that these changes do not affect their performance. These methods do not vectorize because of flow control.

I've run the tier1-3 tests on linux/aarch64 and didn't observe any regressions.

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Issue

JDK-8329077: C2 SuperWord: Add MoveD2L, MoveL2D, MoveF2I, MoveI2F (Enhancement - P4)

Reviewers

Quan Anh Mai (@merykitty - Committer)

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$ git pull https://git.openjdk.org/jdk.git pull/26457/head

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bridgekeeper · 2025-07-24T10:29:47Z

👋 Welcome back galder! A progress list of the required criteria for merging this PR into master will be added to the body of your pull request. There are additional pull request commands available for use with this pull request.

openjdk · 2025-07-24T10:30:43Z

❗ This change is not yet ready to be integrated.
See the Progress checklist in the description for automated requirements.

openjdk · 2025-07-24T10:31:22Z

@galderz The following labels will be automatically applied to this pull request:

core-libs
hotspot-compiler

When this pull request is ready to be reviewed, an "RFR" email will be sent to the corresponding mailing lists. If you would like to change these labels, use the /label pull request command.

mlbridge · 2025-07-24T10:34:37Z

Webrevs

eme64

Thanks for working on this, it looks really good :)

I'll need to do some testing later though.

eme64 · 2025-07-31T12:49:16Z

test/micro/org/openjdk/bench/java/lang/VectorBitConversion.java

@@ -0,0 +1,125 @@
+package org.openjdk.bench.java.lang;


I think this benchmark belongs with the other vectorization benchmarks under
test/micro/org/openjdk/bench/vm/compiler/Vector*

It's not really a language feature, more for vm/compiler

Bhavana-Kilambi · 2025-08-01T10:39:18Z

test/micro/org/openjdk/bench/java/lang/VectorBitConversion.java

@@ -0,0 +1,125 @@
+package org.openjdk.bench.java.lang;
+
+import org.openjdk.jmh.annotations.Benchmark;


This file might also need a Copyright?

merykitty · 2025-08-01T11:58:03Z

VectorNode::is_reinterpret_opcode returns true for Op_ReinterpretHF2S and Op_ReinterpretS2HF, which are very similar to the nodes in this PR, can you add these nodes to that method instead?

Bhavana-Kilambi · 2025-08-01T12:17:03Z

src/hotspot/share/opto/vectornode.cpp

@@ -1815,6 +1827,17 @@ Node* VectorReinterpretNode::Identity(PhaseGVN *phase) {
  return this;
 }

+bool VectorReinterpretNode::implemented(int opc, uint vlen, BasicType src_type, BasicType dst_type) {


opc is not used in this method. Do we need this parameter here?

Yup not needed

Bhavana-Kilambi · 2025-08-01T12:41:09Z

test/micro/org/openjdk/bench/java/lang/VectorBitConversion.java

+    }
+
+    @Benchmark
+    public long[] doubleToLongBits() {


Would something like this be more concise (and maybe more readable as well) -

@Benchmark public long[] doubleToLongBits() { for (int i = 0; i < doubles.length; i++) { resultLongs[i] = Double.doubleToLongBits(doubles[i]); } return resultLongs; }

The loop should still get vectorized (if vectorizable).

Same for other benchmarks.

Maybe but there's a reason why I wrote these benchmark methods this way. Keeping each line doing one thing makes it easier to map each line to the assembly (e.g. perfasm) and related IR nodes (e.g. PrintIdeal). That IMO is more important than the conciseness of the benchmark. What do others think?

Makes sense. Thanks!

Bhavana-Kilambi · 2025-08-01T12:46:01Z

Although this is not in the scope of this patch, but I wonder if we could rename ReinterpretS2HF and ReinterpretHF2S to MoveHF2S and MoveS2HF to keep naming consistent with other types? WDYT @jatin-bhateja

Bhavana-Kilambi · 2025-08-01T12:52:21Z

src/hotspot/share/opto/vectornode.cpp

@@ -1815,6 +1827,17 @@ Node* VectorReinterpretNode::Identity(PhaseGVN *phase) {
  return this;
 }

+bool VectorReinterpretNode::implemented(int opc, uint vlen, BasicType src_type, BasicType dst_type) {
+  if ((src_type == T_FLOAT && dst_type == T_INT) ||


Just a suggestion, do you feel a switch-case could be more readable/clear in this case? Something like this -

bool VectorReinterpretNode::implemented(uint vlen, BasicType src_type, BasicType dst_type) { switch (src_type) { case T_FLOAT: if (dst_type != T_INT) return false; break; case T_INT: if (dst_type != T_FLOAT) return false; break; case T_DOUBLE: if (dst_type != T_LONG) return false; break; case T_LONG: if (dst_type != T_DOUBLE) return false; break; default: return false; } return Matcher::match_rule_supported_auto_vectorization(Op_VectorReinterpret, vlen, dst_type); }

Both options look just fine to me, but I'm happy to re-write it like that if others also feel the same way.

galderz · 2025-08-05T06:05:22Z

VectorNode::is_reinterpret_opcode returns true for Op_ReinterpretHF2S and Op_ReinterpretS2HF, which are very similar to the nodes in this PR, can you add these nodes to that method instead?

You're suggesting to modify is_reinterpret_opcode to be like this, and call that instead of is_move_opcode, right?

bool VectorNode::is_reinterpret_opcode(int opc) {
  switch (opc) {
    case Op_ReinterpretHF2S:
    case Op_ReinterpretS2HF:
    case Op_MoveF2I:
    case Op_MoveD2L:
    case Op_MoveL2D:
    case Op_MoveI2F:
      return true;
    default:
      return false;
  }
}

galderz · 2025-08-05T06:05:35Z

Although this is not in the scope of this patch, but I wonder if we could rename ReinterpretS2HF and ReinterpretHF2S to MoveHF2S and MoveS2HF to keep naming consistent with other types? WDYT @jatin-bhateja

That sounds reasonable to me

merykitty · 2025-08-05T06:32:23Z

You're suggesting to modify is_reinterpret_opcode to be like this, and call that instead of is_move_opcode, right?

Yes, that's right. I believe VectorReinterpret should be implemented for all pairs of vector species where both the input and output species are implemented. So, VectorReinterpretNode::implemented is unnecessary.

chhagedorn · 2025-08-06T08:25:51Z

Internal testing of the latest commit looked good (not a review).

galderz · 2025-08-06T09:45:59Z

@merykitty thanks for the approval. I've run tier1-3 tests for 147633f and they all passed, and the benchmark results are the same as in the description.

Thanks @chhagedorn for running the tests!

eme64 · 2025-08-10T05:23:23Z

src/hotspot/share/opto/superword.cpp

@@ -1632,6 +1632,8 @@ bool SuperWord::implemented(const Node_List* pack, const uint size) const {
      retValue = ReductionNode::implemented(opc, size, arith_type->basic_type());
    } else if (VectorNode::is_convert_opcode(opc)) {
      retValue = VectorCastNode::implemented(opc, size, velt_basic_type(p0->in(1)), velt_basic_type(p0));
+    } else if (VectorNode::is_reinterpret_opcode(opc)) {


How does this affect Op_ReinterpretHF2S that is also in VectorNode::is_reinterpret_opcode?
I'm afraid that we need to test this with hardware or Intel's SDE, to make sure we have it running on a VM that actually supports Float16. Otherwise these instructions may not be used, and hence not tested right.

@galderz Can you run the relevant tests?

Would you run specific tiers in those platforms? Just hotspot compiler? Or individual tests such as ConvF2HFIdealizationTests and TestFloat16ScalarOperations?

Honestly, I don't know, I'd have to do the research myself. Probably focusing on the Float16 tests would be good enough. No other test would really use Float16, so running anything else would not be that useful probably.

I've done some testing on x86_64 and aarch64 and the tests pass.

I also made sure that the test output demonstrated execution of the expected IR rule as per the requirements of each platform.

c7gn.2xlarge Graviton3

============================== Test summary ============================== TEST TOTAL PASS FAIL ERROR SKIP jtreg:test/hotspot/jtreg/compiler/c2/irTests/ConvF2HFIdealizationTests.java 1 1 0 0 0 jtreg:test/hotspot/jtreg/compiler/c2/irTests/TestFloat16ScalarOperations.java 1 1 0 0 0 jtreg:test/hotspot/jtreg/compiler/loopopts/superword/TestCompatibleUseDefTypeSize.java 1 1 0 0 0 ============================== TEST SUCCESS $ tail ConvF2HFIdealizationTests.jtr Messages from Test VM --------------------- [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in test1: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true ----------System.err:(3/35)---------- JavaTest Message: Test complete. result: Passed. Execution successful test result: Passed. Execution successful $ tail TestFloat16ScalarOperations.jtr Messages from Test VM --------------------- [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testDivByPOT: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testMulByTWO: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testInexactFP16ConstantPatterns: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testSNaNFP16ConstantPatterns: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testQNaNFP16ConstantPatterns: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testExactFP16ConstantPatterns: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testRandomFP16ConstantPatternSet1: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testRandomFP16ConstantPatternSet2: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testRounding1: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testRounding2: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testMax: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testAddConstantFolding: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testDivConstantFolding: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testMin: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testMinConstantFolding: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testEliminateIntermediateHF2S: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testDivByOne: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testFMAConstantFolding: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testMaxConstantFolding: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testMul: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testconvF2HFAndS2HF: Feature constraint not met (applyIfCPUFeature): avx512_fp16, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testDiv: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testSqrtConstantFolding: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testSqrt: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testMulConstantFolding: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testFma: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testAdd1: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testAdd2: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testSubConstantFolding: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true [IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testSub: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true ----------System.err:(3/35)---------- JavaTest Message: Test complete. result: Passed. Execution successful test result: Passed. Execution successful

c7i.xlarge Intel(R) Xeon(R) Platinum 8488C (saphire rapids):

============================== Test summary ============================== TEST TOTAL PASS FAIL ERROR SKIP jtreg:test/hotspot/jtreg/compiler/c2/irTests/ConvF2HFIdealizationTests.java 1 1 0 0 0 jtreg:test/hotspot/jtreg/compiler/c2/irTests/TestFloat16ScalarOperations.java 1 1 0 0 0 jtreg:test/hotspot/jtreg/compiler/loopopts/superword/TestCompatibleUseDefTypeSize.java 1 1 0 0 0 ============================== TEST SUCCESS $ tail ConvF2HFIdealizationTests.jtr Messages from Test VM --------------------- [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in test1: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true ----------System.err:(3/35)---------- JavaTest Message: Test complete. result: Passed. Execution successful test result: Passed. Execution successful $ tail TestFloat16ScalarOperations.jtr Messages from Test VM --------------------- [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testDivByPOT: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testMulByTWO: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testInexactFP16ConstantPatterns: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testSNaNFP16ConstantPatterns: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testQNaNFP16ConstantPatterns: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testExactFP16ConstantPatterns: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testRandomFP16ConstantPatternSet1: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testRandomFP16ConstantPatternSet2: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testRounding1: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testRounding2: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testMax: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testAddConstantFolding: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testDivConstantFolding: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testMin: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testMinConstantFolding: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testEliminateIntermediateHF2S: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testDivByOne: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testFMAConstantFolding: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testMaxConstantFolding: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testMul: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testconvF2HFAndS2HF: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testDiv: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testSqrtConstantFolding: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testSqrt: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testMulConstantFolding: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testFma: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testAdd1: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testAdd2: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testSubConstantFolding: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true [IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testSub: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true ----------System.err:(3/35)---------- JavaTest Message: Test complete. result: Passed. Execution successful test result: Passed. Execution successful

Btw, I've noticed that TestFloat16ScalarOperations does not have package definition. Is that an oversight? It runs fine in spite of not having it

Hi, as you mostly touched the auto-vectorization part of c2, could you please run these float16 tests as well (most of these enable auto-vectorization for Float16) -

compiler/vectorization/TestFloat16VectorOperations.java
compiler/vectorization/TestFloatConversionsVectorNaN.java
compiler/vectorization/TestFloatConversionsVector.java
compiler/vectorization/TestFloat16ToFloatConv.java
compiler/vectorization/TestFloat16VectorConvChain.java
compiler/intrinsics/float16/*

galderz added 15 commits July 4, 2025 12:28

floatToRawIntBits: initial impl

f747a0a

floatToRawIntBits: vectorized JMH microbenchmark

6b1a1eb

floatToRawIntBits: add missing @State in benchmark

4a86185

floatToRawIntBits: switch benchmark to float

8666ca0

add floatToIntBits benchmark

e15c143

Support doubleToRawLongBits

61625fe

Add JMH benchmark for doubleTo*LongBits

d69ecad

Add basic IR test

2bace0c

Fix test for vectorized and add floatToRawIntBits

18e8ce2

Add longBitsToDouble and intBitsToFloat

25199da

Merge branch 'master' into topic.fp-bits-vector

cae1f08

Delete IR test because it's already covered by other test

3e527c2

Adjust IR test after adding Move* vector support

7e0e70b

Removed unnecessary assert methods

b6ec784

Rephrase comment

1b8babd

openjdk bot added the rfr Pull request is ready for review label Jul 24, 2025

openjdk bot added hotspot-compiler [email protected] core-libs [email protected] labels Jul 24, 2025

eme64 suggested changes Jul 31, 2025

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Bhavana-Kilambi reviewed Aug 1, 2025

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galderz added 3 commits August 5, 2025 10:04

Refactor and add copyright header

879eddb

Avoid VectorReinterpret::implemented

dde8699

Check at the very least that auto vectorization is supported

147633f

merykitty approved these changes Aug 6, 2025

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eme64 reviewed Aug 10, 2025

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		@@ -0,0 +1,125 @@
		package org.openjdk.bench.java.lang;

		import org.openjdk.jmh.annotations.Benchmark;

8329077: C2 SuperWord: Add MoveD2L, MoveL2D, MoveF2I, MoveI2F #26457

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8329077: C2 SuperWord: Add MoveD2L, MoveL2D, MoveF2I, MoveI2F #26457

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