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f747a0a
floatToRawIntBits: initial impl
galderz Jul 4, 2025
6b1a1eb
floatToRawIntBits: vectorized JMH microbenchmark
galderz Jul 4, 2025
4a86185
floatToRawIntBits: add missing @State in benchmark
galderz Jul 4, 2025
8666ca0
floatToRawIntBits: switch benchmark to float
galderz Jul 4, 2025
e15c143
add floatToIntBits benchmark
galderz Jul 4, 2025
61625fe
Support doubleToRawLongBits
galderz Jul 8, 2025
d69ecad
Add JMH benchmark for doubleTo*LongBits
galderz Jul 8, 2025
2bace0c
Add basic IR test
galderz Jul 21, 2025
18e8ce2
Fix test for vectorized and add floatToRawIntBits
galderz Jul 21, 2025
25199da
Add longBitsToDouble and intBitsToFloat
galderz Jul 22, 2025
cae1f08
Merge branch 'master' into topic.fp-bits-vector
galderz Jul 22, 2025
3e527c2
Delete IR test because it's already covered by other test
galderz Jul 22, 2025
7e0e70b
Adjust IR test after adding Move* vector support
galderz Jul 22, 2025
b6ec784
Removed unnecessary assert methods
galderz Jul 22, 2025
1b8babd
Rephrase comment
galderz Jul 24, 2025
879eddb
Refactor and add copyright header
galderz Aug 5, 2025
dde8699
Avoid VectorReinterpret::implemented
galderz Aug 5, 2025
147633f
Check at the very least that auto vectorization is supported
galderz Aug 5, 2025
cfe998c
Refactor benchmarks to TypeVectorOperations
galderz Aug 21, 2025
89d9bbb
Fix source of data for benchmarks
galderz Aug 22, 2025
01fd5ba
Add more IR node positive assertions
galderz Aug 22, 2025
e7e4d80
Merge branch 'master' into topic.fp-bits-vector
galderz Aug 25, 2025
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2 changes: 2 additions & 0 deletions src/hotspot/share/opto/superword.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1632,6 +1632,8 @@ bool SuperWord::implemented(const Node_List* pack, const uint size) const {
retValue = ReductionNode::implemented(opc, size, arith_type->basic_type());
} else if (VectorNode::is_convert_opcode(opc)) {
retValue = VectorCastNode::implemented(opc, size, velt_basic_type(p0->in(1)), velt_basic_type(p0));
} else if (VectorNode::is_reinterpret_opcode(opc)) {
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How does this affect Op_ReinterpretHF2S that is also in VectorNode::is_reinterpret_opcode?
I'm afraid that we need to test this with hardware or Intel's SDE, to make sure we have it running on a VM that actually supports Float16. Otherwise these instructions may not be used, and hence not tested right.

@galderz Can you run the relevant tests?

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Would you run specific tiers in those platforms? Just hotspot compiler? Or individual tests such as ConvF2HFIdealizationTests and TestFloat16ScalarOperations?

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Honestly, I don't know, I'd have to do the research myself. Probably focusing on the Float16 tests would be good enough. No other test would really use Float16, so running anything else would not be that useful probably.

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I've done some testing on x86_64 and aarch64 and the tests pass.

I also made sure that the test output demonstrated execution of the expected IR rule as per the requirements of each platform.

c7gn.2xlarge Graviton3

==============================
Test summary
==============================
   TEST                                              TOTAL  PASS  FAIL ERROR  SKIP
   jtreg:test/hotspot/jtreg/compiler/c2/irTests/ConvF2HFIdealizationTests.java
                                                         1     1     0     0     0
   jtreg:test/hotspot/jtreg/compiler/c2/irTests/TestFloat16ScalarOperations.java
                                                         1     1     0     0     0
   jtreg:test/hotspot/jtreg/compiler/loopopts/superword/TestCompatibleUseDefTypeSize.java
                                                         1     1     0     0     0
==============================
TEST SUCCESS

$ tail ConvF2HFIdealizationTests.jtr
Messages from Test VM
---------------------
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in test1: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true


----------System.err:(3/35)----------

JavaTest Message: Test complete.

result: Passed. Execution successful


test result: Passed. Execution successful

$ tail TestFloat16ScalarOperations.jtr
Messages from Test VM
---------------------
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testDivByPOT: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testMulByTWO: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testInexactFP16ConstantPatterns: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testSNaNFP16ConstantPatterns: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testQNaNFP16ConstantPatterns: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testExactFP16ConstantPatterns: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testRandomFP16ConstantPatternSet1: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testRandomFP16ConstantPatternSet2: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testRounding1: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testRounding2: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testMax: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testAddConstantFolding: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testDivConstantFolding: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testMin: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testMinConstantFolding: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testEliminateIntermediateHF2S: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testDivByOne: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testFMAConstantFolding: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testMaxConstantFolding: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testMul: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testconvF2HFAndS2HF: Feature constraint not met (applyIfCPUFeature): avx512_fp16, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testDiv: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testSqrtConstantFolding: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testSqrt: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testMulConstantFolding: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testFma: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testAdd1: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testAdd2: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testSubConstantFolding: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true
[IREncodingPrinter] Disabling IR matching for rule 1 of 2 in testSub: None of the feature constraints met (applyIfCPUFeatureOr): avx512_fp16, true, zfh, true


----------System.err:(3/35)----------

JavaTest Message: Test complete.

result: Passed. Execution successful


test result: Passed. Execution successful

c7i.xlarge Intel(R) Xeon(R) Platinum 8488C (saphire rapids):

==============================
Test summary
==============================
   TEST                                              TOTAL  PASS  FAIL ERROR  SKIP
   jtreg:test/hotspot/jtreg/compiler/c2/irTests/ConvF2HFIdealizationTests.java
                                                         1     1     0     0     0
   jtreg:test/hotspot/jtreg/compiler/c2/irTests/TestFloat16ScalarOperations.java
                                                         1     1     0     0     0
   jtreg:test/hotspot/jtreg/compiler/loopopts/superword/TestCompatibleUseDefTypeSize.java
                                                         1     1     0     0     0
==============================
TEST SUCCESS

$ tail ConvF2HFIdealizationTests.jtr
Messages from Test VM
---------------------
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in test1: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true


----------System.err:(3/35)----------

JavaTest Message: Test complete.

result: Passed. Execution successful


test result: Passed. Execution successful

$ tail TestFloat16ScalarOperations.jtr
Messages from Test VM
---------------------
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testDivByPOT: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testMulByTWO: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testInexactFP16ConstantPatterns: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testSNaNFP16ConstantPatterns: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testQNaNFP16ConstantPatterns: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testExactFP16ConstantPatterns: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testRandomFP16ConstantPatternSet1: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testRandomFP16ConstantPatternSet2: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testRounding1: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testRounding2: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testMax: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testAddConstantFolding: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testDivConstantFolding: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testMin: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testMinConstantFolding: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testEliminateIntermediateHF2S: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testDivByOne: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testFMAConstantFolding: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testMaxConstantFolding: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testMul: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testconvF2HFAndS2HF: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testDiv: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testSqrtConstantFolding: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testSqrt: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testMulConstantFolding: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testFma: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testAdd1: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testAdd2: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testSubConstantFolding: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true
[IREncodingPrinter] Disabling IR matching for rule 2 of 2 in testSub: Not all feature constraints are met (applyIfCPUFeatureAnd): fphp, true, asimdhp, true


----------System.err:(3/35)----------

JavaTest Message: Test complete.

result: Passed. Execution successful


test result: Passed. Execution successful

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Btw, I've noticed that TestFloat16ScalarOperations does not have package definition. Is that an oversight? It runs fine in spite of not having it

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Hi, as you mostly touched the auto-vectorization part of c2, could you please run these float16 tests as well (most of these enable auto-vectorization for Float16) -

compiler/vectorization/TestFloat16VectorOperations.java
compiler/vectorization/TestFloatConversionsVectorNaN.java
compiler/vectorization/TestFloatConversionsVector.java
compiler/vectorization/TestFloat16ToFloatConv.java
compiler/vectorization/TestFloat16VectorConvChain.java
compiler/intrinsics/float16/*

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@Bhavana-Kilambi I've run these tests:

  "test/hotspot/jtreg/compiler/c2/irTests/ConvF2HFIdealizationTests.java"
  "test/hotspot/jtreg/compiler/c2/irTests/TestFloat16ScalarOperations.java"
  "test/hotspot/jtreg/compiler/intrinsics/float16/*"
  "test/hotspot/jtreg/compiler/vectorization/TestFloat16ToFloatConv.java"
  "test/hotspot/jtreg/compiler/vectorization/TestFloat16VectorConvChain.java"
  "test/hotspot/jtreg/compiler/vectorization/TestFloat16VectorOperations.java"
  "test/hotspot/jtreg/compiler/vectorization/TestFloatConversionsVector.java"
  "test/hotspot/jtreg/compiler/vectorization/TestFloatConversionsVectorNaN.java"

On x86:

Test results: passed: 11; did not meet platform requirements: 1
(TestFloatConversionsVectorNaN is for riscv)

On graviton 3 aarch64:

Test results: passed: 10; failed: 1; did not meet platform requirements: 1

The failure on aarch64 is already existing issue JDK-8361582

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@galderz Excellent, that's great :)

retValue = Matcher::match_rule_supported_auto_vectorization(Op_VectorReinterpret, size, velt_basic_type(p0));
} else if (VectorNode::is_minmax_opcode(opc) && is_subword_type(velt_basic_type(p0))) {
// Java API for Math.min/max operations supports only int, long, float
// and double types. Thus, avoid generating vector min/max nodes for
Expand Down
4 changes: 4 additions & 0 deletions src/hotspot/share/opto/vectornode.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -992,6 +992,10 @@ bool VectorNode::is_vector_bitwise_not_pattern(Node* n) {

bool VectorNode::is_reinterpret_opcode(int opc) {
switch (opc) {
case Op_MoveF2I:
case Op_MoveD2L:
case Op_MoveL2D:
case Op_MoveI2F:
case Op_ReinterpretHF2S:
case Op_ReinterpretS2HF:
return true;
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -395,7 +395,7 @@ static Object[] test4(int[] a, int[] b) {
// In theory, one would expect this to be a simple 4byte -> 4byte conversion.
// But there is a CmpF and CMove here because we check for isNaN. Plus a MoveF2I.
//
// Would be nice to vectorize: Missing support for CmpF, CMove and MoveF2I.
// Would be nice to vectorize: Missing support for CmpF and CMove.
static Object[] test5(int[] a, float[] b) {
for (int i = 0; i < a.length; i++) {
a[i] = Float.floatToIntBits(b[i]);
Expand All @@ -404,10 +404,11 @@ static Object[] test5(int[] a, float[] b) {
}

@Test
@IR(counts = {IRNode.STORE_VECTOR, "= 0"},
@IR(counts = {IRNode.LOAD_VECTOR_F, "> 0",
IRNode.STORE_VECTOR, "> 0",
IRNode.VECTOR_REINTERPRET, "> 0"},
applyIfPlatform = {"64-bit", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "asimd", "true", "rvv", "true"})
// Missing support for MoveF2I
static Object[] test6(int[] a, float[] b) {
for (int i = 0; i < a.length; i++) {
a[i] = Float.floatToRawIntBits(b[i]);
Expand All @@ -416,10 +417,11 @@ static Object[] test6(int[] a, float[] b) {
}

@Test
@IR(counts = {IRNode.STORE_VECTOR, "= 0"},
@IR(counts = {IRNode.LOAD_VECTOR_I, "> 0",
IRNode.STORE_VECTOR, "> 0",
IRNode.VECTOR_REINTERPRET, "> 0"},
applyIfPlatform = {"64-bit", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "asimd", "true", "rvv", "true"})
// Missing support for MoveI2F
static Object[] test7(int[] a, float[] b) {
for (int i = 0; i < a.length; i++) {
b[i] = Float.intBitsToFloat(a[i]);
Expand All @@ -431,7 +433,7 @@ static Object[] test7(int[] a, float[] b) {
@IR(counts = {IRNode.STORE_VECTOR, "= 0"},
applyIfPlatform = {"64-bit", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "asimd", "true", "rvv", "true"})
// Missing support for Needs CmpD, CMove and MoveD2L
// Missing support to vectorize CmpD and CMove
static Object[] test8(long[] a, double[] b) {
for (int i = 0; i < a.length; i++) {
a[i] = Double.doubleToLongBits(b[i]);
Expand All @@ -440,10 +442,11 @@ static Object[] test8(long[] a, double[] b) {
}

@Test
@IR(counts = {IRNode.STORE_VECTOR, "= 0"},
@IR(counts = {IRNode.LOAD_VECTOR_D, "> 0",
IRNode.STORE_VECTOR, "> 0",
IRNode.VECTOR_REINTERPRET, "> 0"},
applyIfPlatform = {"64-bit", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "asimd", "true", "rvv", "true"})
// Missing support for MoveD2L
static Object[] test9(long[] a, double[] b) {
for (int i = 0; i < a.length; i++) {
a[i] = Double.doubleToRawLongBits(b[i]);
Expand All @@ -452,10 +455,11 @@ static Object[] test9(long[] a, double[] b) {
}

@Test
@IR(counts = {IRNode.STORE_VECTOR, "= 0"},
@IR(counts = {IRNode.LOAD_VECTOR_L, "> 0",
IRNode.STORE_VECTOR, "> 0",
IRNode.VECTOR_REINTERPRET, "> 0"},
applyIfPlatform = {"64-bit", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "asimd", "true", "rvv", "true"})
// Missing support for MoveL2D
static Object[] test10(long[] a, double[] b) {
for (int i = 0; i < a.length; i++) {
b[i] = Double.longBitsToDouble(a[i]);
Expand Down
43 changes: 43 additions & 0 deletions test/micro/org/openjdk/bench/vm/compiler/TypeVectorOperations.java
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2019, 2024, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2025 IBM Corporation. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
Expand Down Expand Up @@ -262,13 +263,41 @@ public void convertD2L() {
}
}

@Benchmark
public void convertD2LBits() {
for (int i = 0; i < COUNT; i++) {
resL[i] = Double.doubleToLongBits(doubles[i]);
}
}

@Benchmark
public void convertD2LBitsRaw() {
for (int i = 0; i < COUNT; i++) {
resL[i] = Double.doubleToRawLongBits(doubles[i]);
}
}

@Benchmark
public void convertF2I() {
for (int i = 0; i < COUNT; i++) {
resI[i] = (int) floats[i];
}
}

@Benchmark
public void convertF2IBits() {
for (int i = 0; i < COUNT; i++) {
resI[i] = Float.floatToIntBits(floats[i]);
}
}

@Benchmark
public void convertF2IBitsRaw() {
for (int i = 0; i < COUNT; i++) {
resI[i] = (int) Float.floatToRawIntBits(floats[i]);
}
}

@Benchmark
public void convertF2B() {
for (int i = 0; i < COUNT; i++) {
Expand Down Expand Up @@ -304,6 +333,13 @@ public void convertI2F() {
}
}

@Benchmark
public void convertIBits2F() {
for (int i = 0; i < COUNT; i++) {
resF[i] = Float.intBitsToFloat(ints[i]);
}
}

@Benchmark
public void convertI2D() {
for (int i = 0; i < COUNT; i++) {
Expand All @@ -325,6 +361,13 @@ public void convertL2D() {
}
}

@Benchmark
public void convertLBits2D() {
for (int i = 0; i < COUNT; i++) {
resD[i] = Double.longBitsToDouble(longs[i]);
}
}

@Benchmark
public void convertL2B() {
for (int i = 0; i < COUNT; i++) {
Expand Down