feat(backends): add binutils generator for RISC-V opcode tables #1072
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Implement a comprehensive binutils generator that creates binutils-compatible opcode table entries from RISC-V UDB instruction definitions. The generator produces C source files and headers following the binutils-gdb format used in opcodes/riscv-opc.c. Key features: - Extension-aware instruction class mapping with built-in and custom support - Operand format conversion from UDB assembly syntax to binutils format - MATCH/MASK constant generation with proper bit manipulation - Configurable architecture support (RV32, RV64, BOTH) - Comprehensive documentation and integration guidelines Components: - binutils_generator.py: Main generator with CLI interface - binutils_parser.py: Core parsing and conversion logic - extract_riscv_operand_bits.py: Operand bit extraction utilities - insn_class_config.py: Extension to instruction class mappings - naming_config.py: User-defined naming and preference configurations - README.md: Comprehensive documentation and usage examples Signed-off-by: Afonso Oliveira <[email protected]>
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IMPORTANT: The scope of this PR is not to fully generate Binutils, rather to make the development of new/custom extensions much faster as it automates a big chunk of that process.
Implement a binutils generator that creates binutils-compatible opcode table entries from RISC-V UDB instruction definitions. The generator produces C source files and headers following the binutils-gdb format used in opcodes/riscv-opc.c.
Key features:
Components:
This is a WiP PR and I know I am creating tech debt on my own PRs, but I guess I am more keen on creating new solutions than finishing