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31 changes: 21 additions & 10 deletions src/codegen/c.zig
Original file line number Diff line number Diff line change
Expand Up @@ -5772,16 +5772,27 @@ fn airAsm(f: *Function, inst: Air.Inst.Index) !CValue {
assert(name.len != 0);

const target = &f.object.dg.mod.resolved_target.result;
if (target.cpu.arch.isMIPS() and name[0] == 'r') {
// GCC uses "$N" for register names instead of "rN" used by Zig.
var c_name_buf: [4]u8 = undefined;
const c_name = (&c_name_buf)[0..name.len];
@memcpy(c_name, name);
c_name_buf[0] = '$';

try w.print(" {f}", .{fmtStringLiteral(c_name, null)});
(try w.writableArray(1))[0] = ',';
continue;
if (target.cpu.arch.isMIPS()) {
if (name[0] == 'r') {
// C uses "$N" for register names instead of "rN" used by Zig.
var c_name_buf: [4]u8 = undefined;
const c_name = (&c_name_buf)[0..name.len];
@memcpy(c_name, name);
c_name_buf[0] = '$';

try w.print(" {f}", .{fmtStringLiteral(c_name, null)});
(try w.writableArray(1))[0] = ',';
continue;
} else if (mem.startsWith(u8, name, "fcc") or name[0] == 'w' or name[0] == 'f') {
// C requires a "$" prefix before register names.
var c_name_buf: [6]u8 = undefined;
c_name_buf[0] = '$';
@memcpy((&c_name_buf)[1..][0..name.len], name);

try w.print(" {f}", .{fmtStringLiteral((&c_name_buf)[0 .. 1 + name.len], null)});
(try w.writableArray(1))[0] = ',';
continue;
}
Comment on lines +5776 to +5795
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Some of my recent work led me to the realization that Alpha also uses $-prefixed registers... so we'll need this code for more targets.

To make it a bit more maintainable, I would suggest moving c_name_buf out of the target check and just giving it a "big enough" size like 64, renaming name to field_name, and then:

const name = if (target.cpu.arch.isMIPS())
    // ... write into c_name_buf and return a slice of it ...
else
    field_name;

Then we also don't need to duplicate the trailing writing logic.

}

try w.print(" {f}", .{fmtStringLiteral(name, null)});
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